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perf vendor events intel: Update skylake events to v58

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Update skylake events to v58 released in:
625fb75073

Improves documentation.

Event json automatically generated by:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py

Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Samantha Alt <samantha.alt@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240214011820.644458-12-irogers@google.com
This commit is contained in:
Ian Rogers
2024-02-13 17:18:00 -08:00
committed by Namhyung Kim
parent 9626368d42
commit c31d718ca2
4 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
tools/perf/pmu-events/arch/x86/mapfile.csv
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@@ -29,7 +29,7 @@ GenuineIntel-6-2A,v19,sandybridge,core
GenuineIntel-6-8F,v1.17,sapphirerapids,core
GenuineIntel-6-AF,v1.01,sierraforest,core
GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v57,skylake,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v58,skylake,core
GenuineIntel-6-55-[01234],v1.32,skylakex,core
GenuineIntel-6-86,v1.21,snowridgex,core
GenuineIntel-6-8[CD],v1.13,tigerlake,core
1 Family-model Version Filename EventType
29 GenuineIntel-6-8F v1.17 sapphirerapids core
30 GenuineIntel-6-AF v1.01 sierraforest core
31 GenuineIntel-6-(37|4A|4C|4D|5A) v15 silvermont core
32 GenuineIntel-6-(4E|5E|8E|9E|A5|A6) v57 v58 skylake core
33 GenuineIntel-6-55-[01234] v1.32 skylakex core
34 GenuineIntel-6-86 v1.21 snowridgex core
35 GenuineIntel-6-8[CD] v1.13 tigerlake core

2
tools/perf/pmu-events/arch/x86/skylake/memory.json
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@@ -1008,7 +1008,7 @@
"BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
"PEBS": "2",
"PublicDescription": "Number of times RTM abort was triggered.",
"SampleAfterValue": "2000003",
"UMask": "0x4"

2
tools/perf/pmu-events/arch/x86/skylake/pipeline.json
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@@ -387,7 +387,7 @@
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.NOP",
"PEBS": "1",
"PEBS": "2",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},

2
tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json
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@@ -205,7 +205,7 @@
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
"PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake microarchitecture.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},