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drm/i915/xe2lpd: Add display power well

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Add Display Power Well for Xe2_LPD. It's mostly the same as Xe_LPD+,
so reuse the code. PGPICA1 contains type-C capable port slices
which requires the well to power powered up, so add new power well
definition for it.

The DC_OFF fake power well will be added in a follow up commit.

v2: Do not rmw as bit 31 is the only R/W bit in the register (Matt Roper)

BSpec: 68886
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-20-lucas.demarchi@intel.com
This commit is contained in:
Ravi Kumar Vodapalli
2023-09-19 12:21:26 -07:00
committed by Lucas De Marchi
parent 394b4b7df9
commit c2d9d8e7ee
4 changed files with 82 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
drivers/gpu/drm/i915/display/intel_display_power_map.c
View File

@@ -1536,6 +1536,38 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
};
I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
POWER_DOMAIN_PORT_DDI_LANES_TC1,
POWER_DOMAIN_PORT_DDI_LANES_TC2,
POWER_DOMAIN_PORT_DDI_LANES_TC3,
POWER_DOMAIN_PORT_DDI_LANES_TC4,
POWER_DOMAIN_AUX_USBC1,
POWER_DOMAIN_AUX_USBC2,
POWER_DOMAIN_AUX_USBC3,
POWER_DOMAIN_AUX_USBC4,
POWER_DOMAIN_AUX_TBT1,
POWER_DOMAIN_AUX_TBT2,
POWER_DOMAIN_AUX_TBT3,
POWER_DOMAIN_AUX_TBT4,
POWER_DOMAIN_INIT);
static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
{
.instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
&xe2lpd_pwdoms_pica_tc,
.id = DISP_PW_ID_NONE),
),
.ops = &xe2lpd_pica_power_well_ops,
},
};
static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
};
static void init_power_well_domains(const struct i915_power_well_instance *inst,
struct i915_power_well *power_well)
{
@@ -1643,7 +1675,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
return 0;
}
if (DISPLAY_VER(i915) >= 14)
if (DISPLAY_VER(i915) >= 20)
return set_power_wells(power_domains, xe2lpd_power_wells);
else if (DISPLAY_VER(i915) >= 14)
return set_power_wells(power_domains, xelpdp_power_wells);
else if (IS_DG2(i915))
return set_power_wells(power_domains, xehpd_power_wells);

41
drivers/gpu/drm/i915/display/intel_display_power_well.c
View File

@@ -1833,6 +1833,40 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
}
static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL,
XE2LPD_PICA_CTL_POWER_REQUEST);
if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
}
}
static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL, 0);
if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
}
}
static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
XE2LPD_PICA_CTL_POWER_STATUS;
}
const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = i9xx_always_on_power_well_noop,
@@ -1952,3 +1986,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
.disable = xelpdp_aux_power_well_disable,
.is_enabled = xelpdp_aux_power_well_enabled,
};
const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = xe2lpd_pica_power_well_enable,
.disable = xe2lpd_pica_power_well_disable,
.is_enabled = xe2lpd_pica_power_well_enabled,
};

1
drivers/gpu/drm/i915/display/intel_display_power_well.h
View File

@@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops;
extern const struct i915_power_well_ops icl_ddi_power_well_ops;
extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
#endif

5
drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
View File

@@ -86,4 +86,9 @@
_XELPDP_DP_AUX_CH_DATA(__xe2lpd_aux_ch_idx(aux_ch), i) : \
_XELPDP_DP_AUX_CH_DATA(aux_ch, i))
/* PICA Power Well Control */
#define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04)
#define XE2LPD_PICA_CTL_POWER_REQUEST REG_BIT(31)
#define XE2LPD_PICA_CTL_POWER_STATUS REG_BIT(30)
#endif /* __INTEL_DP_AUX_REGS_H__ */