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riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110

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Add USB and PCIe PHY dts nodes for the StarFive JH7110 SoC.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Minda Chen
2023-07-26 03:06:08 -07:00
committed by Conor Dooley
parent f2b539af57
commit c2a10081c0
1 changed files with 21 additions and 0 deletions
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21
arch/riscv/boot/dts/starfive/jh7110.dtsi
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@@ -446,6 +446,27 @@ i2c2: i2c@10050000 {
status = "disabled";
};
usbphy0: phy@10200000 {
compatible = "starfive,jh7110-usb-phy";
reg = <0x0 0x10200000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
<&stgcrg JH7110_STGCLK_USB0_APP_125>;
clock-names = "125m", "app_125m";
#phy-cells = <0>;
};
pciephy0: phy@10210000 {
compatible = "starfive,jh7110-pcie-phy";
reg = <0x0 0x10210000 0x0 0x10000>;
#phy-cells = <0>;
};
pciephy1: phy@10220000 {
compatible = "starfive,jh7110-pcie-phy";
reg = <0x0 0x10220000 0x0 0x10000>;
#phy-cells = <0>;
};
stgcrg: clock-controller@10230000 {
compatible = "starfive,jh7110-stgcrg";
reg = <0x0 0x10230000 0x0 0x10000>;