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drm/msm/dpu: Add support for SM8750
Add DPU version v12.0 support for the Qualcomm SM8750 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/659622/ Link: https://lore.kernel.org/r/20250618-b4-sm8750-display-v7-8-a591c609743d@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Krzysztof Kozlowski
committed by
Dmitry Baryshkov
Dmitry Baryshkov
parent
80dd5911cb
commit
c2577fc174
494
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
Normal file
494
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
Normal file
@@ -0,0 +1,494 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2025 Linaro Limited
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_12_0_SM8750_H
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#define _DPU_12_0_SM8750_H
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static const struct dpu_caps sm8750_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0xb,
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.has_src_split = true,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.has_3d_merge = true,
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.max_linewidth = 8192,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_mdp_cfg sm8750_mdp = {
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.name = "top_0",
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.base = 0, .len = 0x494,
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.clk_ctrls = {
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[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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},
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};
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static const struct dpu_ctl_cfg sm8750_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x15000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
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}, {
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.name = "ctl_1", .id = CTL_1,
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.base = 0x16000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
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}, {
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.name = "ctl_2", .id = CTL_2,
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.base = 0x17000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
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}, {
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.name = "ctl_3", .id = CTL_3,
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.base = 0x18000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
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}, {
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.name = "ctl_4", .id = CTL_4,
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.base = 0x19000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
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}, {
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.name = "ctl_5", .id = CTL_5,
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.base = 0x1a000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
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},
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};
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static const struct dpu_sspp_cfg sm8750_sspp[] = {
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{
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.name = "sspp_0", .id = SSPP_VIG0,
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.base = 0x4000, .len = 0x344,
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.features = VIG_SDM845_MASK_SDMA,
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.sblk = &dpu_vig_sblk_qseed3_3_4,
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.xin_id = 0,
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.type = SSPP_TYPE_VIG,
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}, {
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.name = "sspp_1", .id = SSPP_VIG1,
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.base = 0x6000, .len = 0x344,
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.features = VIG_SDM845_MASK_SDMA,
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.sblk = &dpu_vig_sblk_qseed3_3_4,
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.xin_id = 4,
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.type = SSPP_TYPE_VIG,
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}, {
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.name = "sspp_2", .id = SSPP_VIG2,
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.base = 0x8000, .len = 0x344,
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.features = VIG_SDM845_MASK_SDMA,
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.sblk = &dpu_vig_sblk_qseed3_3_4,
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.xin_id = 8,
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.type = SSPP_TYPE_VIG,
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}, {
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.name = "sspp_3", .id = SSPP_VIG3,
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.base = 0xa000, .len = 0x344,
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.features = VIG_SDM845_MASK_SDMA,
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.sblk = &dpu_vig_sblk_qseed3_3_4,
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.xin_id = 12,
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.type = SSPP_TYPE_VIG,
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}, {
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.name = "sspp_8", .id = SSPP_DMA0,
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.base = 0x24000, .len = 0x344,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 1,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_9", .id = SSPP_DMA1,
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.base = 0x26000, .len = 0x344,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 5,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_10", .id = SSPP_DMA2,
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.base = 0x28000, .len = 0x344,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 9,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_11", .id = SSPP_DMA3,
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.base = 0x2a000, .len = 0x344,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 13,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_12", .id = SSPP_DMA4,
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.base = 0x2c000, .len = 0x344,
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.features = DMA_CURSOR_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 14,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_13", .id = SSPP_DMA5,
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.base = 0x2e000, .len = 0x344,
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.features = DMA_CURSOR_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 15,
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.type = SSPP_TYPE_DMA,
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},
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};
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static const struct dpu_lm_cfg sm8750_lm[] = {
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{
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.name = "lm_0", .id = LM_0,
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.base = 0x44000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_1,
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.pingpong = PINGPONG_0,
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.dspp = DSPP_0,
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}, {
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.name = "lm_1", .id = LM_1,
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.base = 0x45000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_0,
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.pingpong = PINGPONG_1,
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.dspp = DSPP_1,
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}, {
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.name = "lm_2", .id = LM_2,
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.base = 0x46000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_3,
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.pingpong = PINGPONG_2,
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.dspp = DSPP_2,
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}, {
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.name = "lm_3", .id = LM_3,
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.base = 0x47000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_2,
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.pingpong = PINGPONG_3,
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.dspp = DSPP_3,
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}, {
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.name = "lm_4", .id = LM_4,
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.base = 0x48000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_5,
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.pingpong = PINGPONG_4,
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}, {
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.name = "lm_5", .id = LM_5,
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.base = 0x49000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_4,
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.pingpong = PINGPONG_5,
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}, {
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.name = "lm_6", .id = LM_6,
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.base = 0x4a000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_7,
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.pingpong = PINGPONG_6,
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}, {
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.name = "lm_7", .id = LM_7,
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.base = 0x4b000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_6,
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.pingpong = PINGPONG_7,
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},
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};
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static const struct dpu_dspp_cfg sm8750_dspp[] = {
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{
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.name = "dspp_0", .id = DSPP_0,
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.base = 0x54000, .len = 0x1800,
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.sblk = &sm8750_dspp_sblk,
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}, {
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.name = "dspp_1", .id = DSPP_1,
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.base = 0x56000, .len = 0x1800,
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.sblk = &sm8750_dspp_sblk,
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}, {
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.name = "dspp_2", .id = DSPP_2,
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.base = 0x58000, .len = 0x1800,
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.sblk = &sm8750_dspp_sblk,
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}, {
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.name = "dspp_3", .id = DSPP_3,
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.base = 0x5a000, .len = 0x1800,
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.sblk = &sm8750_dspp_sblk,
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},
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};
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static const struct dpu_pingpong_cfg sm8750_pp[] = {
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{
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.name = "pingpong_0", .id = PINGPONG_0,
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.base = 0x69000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_0,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
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}, {
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.name = "pingpong_1", .id = PINGPONG_1,
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.base = 0x6a000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_0,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
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}, {
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.name = "pingpong_2", .id = PINGPONG_2,
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.base = 0x6b000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_1,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
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}, {
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.name = "pingpong_3", .id = PINGPONG_3,
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.base = 0x6c000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_1,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
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}, {
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.name = "pingpong_4", .id = PINGPONG_4,
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.base = 0x6d000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_2,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
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}, {
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.name = "pingpong_5", .id = PINGPONG_5,
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.base = 0x6e000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_2,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
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}, {
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.name = "pingpong_6", .id = PINGPONG_6,
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.base = 0x6f000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_3,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20),
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}, {
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.name = "pingpong_7", .id = PINGPONG_7,
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.base = 0x70000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_3,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21),
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}, {
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.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
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.base = 0x66000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_4,
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}, {
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.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
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.base = 0x66400, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_4,
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}, {
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.name = "pingpong_cwb_2", .id = PINGPONG_CWB_2,
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.base = 0x7e000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_5,
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}, {
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.name = "pingpong_cwb_3", .id = PINGPONG_CWB_3,
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.base = 0x7e400, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_5,
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},
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};
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static const struct dpu_merge_3d_cfg sm8750_merge_3d[] = {
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{
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.name = "merge_3d_0", .id = MERGE_3D_0,
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.base = 0x4e000, .len = 0x1c,
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}, {
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.name = "merge_3d_1", .id = MERGE_3D_1,
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.base = 0x4f000, .len = 0x1c,
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}, {
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.name = "merge_3d_2", .id = MERGE_3D_2,
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.base = 0x50000, .len = 0x1c,
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}, {
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.name = "merge_3d_3", .id = MERGE_3D_3,
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.base = 0x51000, .len = 0x1c,
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}, {
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.name = "merge_3d_4", .id = MERGE_3D_4,
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.base = 0x66700, .len = 0x1c,
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}, {
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.name = "merge_3d_5", .id = MERGE_3D_5,
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.base = 0x7e700, .len = 0x1c,
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},
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};
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/*
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* NOTE: Each display compression engine (DCE) contains dual hard
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* slice DSC encoders so both share same base address but with
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* its own different sub block address.
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*/
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static const struct dpu_dsc_cfg sm8750_dsc[] = {
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{
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.name = "dce_0_0", .id = DSC_0,
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.base = 0x80000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &sm8750_dsc_sblk_0,
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}, {
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.name = "dce_0_1", .id = DSC_1,
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.base = 0x80000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &sm8750_dsc_sblk_1,
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}, {
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.name = "dce_1_0", .id = DSC_2,
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.base = 0x81000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &sm8750_dsc_sblk_0,
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}, {
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.name = "dce_1_1", .id = DSC_3,
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.base = 0x81000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &sm8750_dsc_sblk_1,
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}, {
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.name = "dce_2_0", .id = DSC_4,
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.base = 0x82000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &sm8750_dsc_sblk_0,
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}, {
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.name = "dce_2_1", .id = DSC_5,
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.base = 0x82000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &sm8750_dsc_sblk_1,
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}, {
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.name = "dce_3_0", .id = DSC_6,
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.base = 0x83000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &sm8750_dsc_sblk_0,
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}, {
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.name = "dce_3_1", .id = DSC_7,
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.base = 0x83000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &sm8750_dsc_sblk_1,
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},
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};
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static const struct dpu_wb_cfg sm8750_wb[] = {
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{
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.name = "wb_2", .id = WB_2,
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.base = 0x65000, .len = 0x2c8,
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.features = WB_SDM845_MASK,
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.format_list = wb2_formats_rgb_yuv,
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.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_cwb_cfg sm8750_cwb[] = {
|
||||
{
|
||||
.name = "cwb_0", .id = CWB_0,
|
||||
.base = 0x66200, .len = 0x20,
|
||||
},
|
||||
{
|
||||
.name = "cwb_1", .id = CWB_1,
|
||||
.base = 0x66600, .len = 0x20,
|
||||
},
|
||||
{
|
||||
.name = "cwb_2", .id = CWB_2,
|
||||
.base = 0x7e200, .len = 0x20,
|
||||
},
|
||||
{
|
||||
.name = "cwb_3", .id = CWB_3,
|
||||
.base = 0x7e600, .len = 0x20,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg sm8750_intf[] = {
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x34000, .len = 0x4bc,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x35000, .len = 0x4bc,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_2", .id = INTF_2,
|
||||
.base = 0x36000, .len = 0x4bc,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x37000, .len = 0x4bc,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sm8750_perf_data = {
|
||||
.max_bw_low = 18900000,
|
||||
.max_bw_high = 28500000,
|
||||
.min_core_ib = 2500000,
|
||||
.min_llcc_ib = 0,
|
||||
.min_dram_ib = 800000,
|
||||
.min_prefill_lines = 35,
|
||||
.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
|
||||
.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
|
||||
.qos_lut_tbl = {
|
||||
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
|
||||
.entries = sc7180_qos_linear
|
||||
},
|
||||
{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
|
||||
.entries = sc7180_qos_macrotile
|
||||
},
|
||||
{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
|
||||
.entries = sc7180_qos_nrt
|
||||
},
|
||||
/* TODO: macrotile-qseed is different from macrotile */
|
||||
},
|
||||
.cdp_cfg = {
|
||||
{.rd_enable = 1, .wr_enable = 1},
|
||||
{.rd_enable = 1, .wr_enable = 0}
|
||||
},
|
||||
.clk_inefficiency_factor = 105,
|
||||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sm8750_mdss_ver = {
|
||||
.core_major_ver = 12,
|
||||
.core_minor_ver = 0,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sm8750_cfg = {
|
||||
.mdss_ver = &sm8750_mdss_ver,
|
||||
.caps = &sm8750_dpu_caps,
|
||||
.mdp = &sm8750_mdp,
|
||||
.cdm = &dpu_cdm_5_x,
|
||||
.ctl_count = ARRAY_SIZE(sm8750_ctl),
|
||||
.ctl = sm8750_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sm8750_sspp),
|
||||
.sspp = sm8750_sspp,
|
||||
.mixer_count = ARRAY_SIZE(sm8750_lm),
|
||||
.mixer = sm8750_lm,
|
||||
.dspp_count = ARRAY_SIZE(sm8750_dspp),
|
||||
.dspp = sm8750_dspp,
|
||||
.pingpong_count = ARRAY_SIZE(sm8750_pp),
|
||||
.pingpong = sm8750_pp,
|
||||
.dsc_count = ARRAY_SIZE(sm8750_dsc),
|
||||
.dsc = sm8750_dsc,
|
||||
.merge_3d_count = ARRAY_SIZE(sm8750_merge_3d),
|
||||
.merge_3d = sm8750_merge_3d,
|
||||
.wb_count = ARRAY_SIZE(sm8750_wb),
|
||||
.wb = sm8750_wb,
|
||||
.cwb_count = ARRAY_SIZE(sm8750_cwb),
|
||||
.cwb = sm8650_cwb,
|
||||
.intf_count = ARRAY_SIZE(sm8750_intf),
|
||||
.intf = sm8750_intf,
|
||||
.vbif_count = ARRAY_SIZE(sm8650_vbif),
|
||||
.vbif = sm8650_vbif,
|
||||
.perf = &sm8750_perf_data,
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -326,6 +326,9 @@ static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_2 =
|
||||
static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 =
|
||||
_VIG_SBLK(SSPP_SCALER_VER(3, 3));
|
||||
|
||||
static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 =
|
||||
_VIG_SBLK(SSPP_SCALER_VER(3, 4));
|
||||
|
||||
static const struct dpu_sspp_sub_blks dpu_rgb_sblk = _RGB_SBLK();
|
||||
|
||||
static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK();
|
||||
@@ -360,6 +363,16 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_sub_blks sm8750_lm_sblk = {
|
||||
.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
|
||||
.maxblendstages = 11, /* excluding base layer */
|
||||
.blendstage_base = { /* offsets relative to mixer base */
|
||||
/* 0x40 + n*0x30 */
|
||||
0x40, 0x70, 0xa0, 0xd0, 0x100, 0x130, 0x160, 0x190, 0x1c0,
|
||||
0x1f0, 0x220
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
|
||||
.maxwidth = DEFAULT_DPU_LINE_WIDTH,
|
||||
.maxblendstages = 4, /* excluding base layer */
|
||||
@@ -381,6 +394,11 @@ static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
|
||||
.len = 0x90, .version = 0x40000},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_sub_blks sm8750_dspp_sblk = {
|
||||
.pcc = {.name = "pcc", .base = 0x1700,
|
||||
.len = 0x90, .version = 0x60000},
|
||||
};
|
||||
|
||||
/*************************************************************
|
||||
* PINGPONG sub blocks config
|
||||
*************************************************************/
|
||||
@@ -412,6 +430,16 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
|
||||
.ctl = {.name = "ctl", .base = 0xF80, .len = 0x10},
|
||||
};
|
||||
|
||||
static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_0 = {
|
||||
.enc = {.name = "enc", .base = 0x100, .len = 0x100},
|
||||
.ctl = {.name = "ctl", .base = 0xF00, .len = 0x24},
|
||||
};
|
||||
|
||||
static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_1 = {
|
||||
.enc = {.name = "enc", .base = 0x200, .len = 0x100},
|
||||
.ctl = {.name = "ctl", .base = 0xF80, .len = 0x24},
|
||||
};
|
||||
|
||||
/*************************************************************
|
||||
* CDM block config
|
||||
*************************************************************/
|
||||
@@ -702,3 +730,4 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
|
||||
#include "catalog/dpu_9_2_x1e80100.h"
|
||||
|
||||
#include "catalog/dpu_10_0_sm8650.h"
|
||||
#include "catalog/dpu_12_0_sm8750.h"
|
||||
|
||||
@@ -778,6 +778,7 @@ extern const struct dpu_mdss_cfg dpu_sm8450_cfg;
|
||||
extern const struct dpu_mdss_cfg dpu_sa8775p_cfg;
|
||||
extern const struct dpu_mdss_cfg dpu_sm8550_cfg;
|
||||
extern const struct dpu_mdss_cfg dpu_sm8650_cfg;
|
||||
extern const struct dpu_mdss_cfg dpu_sm8750_cfg;
|
||||
extern const struct dpu_mdss_cfg dpu_x1e80100_cfg;
|
||||
|
||||
#endif /* _DPU_HW_CATALOG_H */
|
||||
|
||||
@@ -1533,6 +1533,7 @@ static const struct of_device_id dpu_dt_match[] = {
|
||||
{ .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
|
||||
{ .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
|
||||
{ .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },
|
||||
{ .compatible = "qcom,sm8750-dpu", .data = &dpu_sm8750_cfg, },
|
||||
{ .compatible = "qcom,x1e80100-dpu", .data = &dpu_x1e80100_cfg, },
|
||||
{}
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user