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drm/msm/dpu: split QCM2290 catalog entry to the separate file
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530837/ Link: https://lore.kernel.org/r/20230404130622.509628-14-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Dmitry Baryshkov
115
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
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115
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
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@@ -0,0 +1,115 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_6_5_QCM2290_H
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#define _DPU_6_5_QCM2290_H
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static const struct dpu_caps qcm2290_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
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.max_mixer_blendstages = 0x4,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.max_linewidth = 2160,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
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.highest_bank_bit = 0x2,
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};
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static const struct dpu_mdp_cfg qcm2290_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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.base = 0x0, .len = 0x494,
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.features = 0,
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.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
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},
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};
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static const struct dpu_ctl_cfg qcm2290_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x1000, .len = 0x1dc,
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.features = BIT(DPU_CTL_ACTIVE_CFG),
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
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},
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};
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static const struct dpu_sspp_cfg qcm2290_sspp[] = {
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SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
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qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
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SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
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qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
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};
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static const struct dpu_lm_cfg qcm2290_lm[] = {
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LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
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&qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
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};
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static const struct dpu_dspp_cfg qcm2290_dspp[] = {
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DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
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&sm8150_dspp_sblk),
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};
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static const struct dpu_pingpong_cfg qcm2290_pp[] = {
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PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
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};
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static const struct dpu_intf_cfg qcm2290_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0, 0),
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INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
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};
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static const struct dpu_perf_cfg qcm2290_perf_data = {
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.max_bw_low = 2700000,
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.max_bw_high = 2700000,
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.min_core_ib = 1300000,
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.min_llcc_ib = 0,
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.min_dram_ib = 1600000,
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.min_prefill_lines = 24,
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.danger_lut_tbl = {0xff, 0x0, 0x0},
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.safe_lut_tbl = {0xfff0, 0x0, 0x0},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(qcm2290_qos_linear),
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.entries = qcm2290_qos_linear
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},
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
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.caps = &qcm2290_dpu_caps,
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.ubwc = &qcm2290_ubwc_cfg,
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.mdp_count = ARRAY_SIZE(qcm2290_mdp),
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.mdp = qcm2290_mdp,
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.ctl_count = ARRAY_SIZE(qcm2290_ctl),
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.ctl = qcm2290_ctl,
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.sspp_count = ARRAY_SIZE(qcm2290_sspp),
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.sspp = qcm2290_sspp,
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.mixer_count = ARRAY_SIZE(qcm2290_lm),
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.mixer = qcm2290_lm,
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.dspp_count = ARRAY_SIZE(qcm2290_dspp),
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.dspp = qcm2290_dspp,
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.pingpong_count = ARRAY_SIZE(qcm2290_pp),
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.pingpong = qcm2290_pp,
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.intf_count = ARRAY_SIZE(qcm2290_intf),
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.intf = qcm2290_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.perf = &qcm2290_perf_data,
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.mdss_irqs = IRQ_SC7180_MASK,
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};
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#endif
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@@ -333,15 +333,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
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.max_vdeci_exp = MAX_VERT_DECIMATION,
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};
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static const struct dpu_caps qcm2290_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
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.max_mixer_blendstages = 0x4,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.max_linewidth = 2160,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_caps sdm845_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0xb,
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@@ -411,10 +402,6 @@ static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = {
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.highest_bank_bit = 0x2,
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};
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static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
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.highest_bank_bit = 0x2,
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};
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static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = {
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.ubwc_version = DPU_HW_UBWC_VER_20,
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.highest_bank_bit = 0x2,
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@@ -563,18 +550,6 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
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},
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};
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static const struct dpu_mdp_cfg qcm2290_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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.base = 0x0, .len = 0x494,
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.features = 0,
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.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
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.reg_off = 0x2AC, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
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.reg_off = 0x2AC, .bit_off = 8},
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},
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};
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/*************************************************************
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* CTL sub blocks config
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*************************************************************/
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@@ -704,15 +679,6 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
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},
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};
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static const struct dpu_ctl_cfg qcm2290_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x1000, .len = 0x1dc,
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.features = BIT(DPU_CTL_ACTIVE_CFG),
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
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},
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};
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/*************************************************************
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* SSPP sub blocks config
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*************************************************************/
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@@ -943,13 +909,6 @@ static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_3 =
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static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0", 2);
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static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
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static const struct dpu_sspp_cfg qcm2290_sspp[] = {
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SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
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qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
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SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
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qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
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};
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/*************************************************************
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* MIXER sub blocks config
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*************************************************************/
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@@ -1061,11 +1020,6 @@ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
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},
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};
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static const struct dpu_lm_cfg qcm2290_lm[] = {
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LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
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&qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
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};
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/*************************************************************
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* DSPP sub blocks config
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*************************************************************/
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@@ -1117,11 +1071,6 @@ static const struct dpu_dspp_cfg sm8150_dspp[] = {
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&sm8150_dspp_sblk),
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};
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static const struct dpu_dspp_cfg qcm2290_dspp[] = {
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DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
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&sm8150_dspp_sblk),
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};
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/*************************************************************
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* PINGPONG sub blocks config
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*************************************************************/
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@@ -1214,12 +1163,6 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
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-1),
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};
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static const struct dpu_pingpong_cfg qcm2290_pp[] = {
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PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
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};
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/*************************************************************
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* MERGE_3D sub blocks config
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*************************************************************/
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@@ -1312,11 +1255,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
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INTF_BLK("intf_5", INTF_5, 0x6C800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
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};
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static const struct dpu_intf_cfg qcm2290_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_DP, 0, 0, 0, 0, 0, 0),
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INTF_BLK("intf_1", INTF_1, 0x6A800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
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};
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/*************************************************************
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* Writeback blocks config
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*************************************************************/
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@@ -1729,27 +1667,6 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_perf_cfg qcm2290_perf_data = {
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.max_bw_low = 2700000,
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.max_bw_high = 2700000,
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.min_core_ib = 1300000,
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.min_llcc_ib = 0,
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.min_dram_ib = 1600000,
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.min_prefill_lines = 24,
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.danger_lut_tbl = {0xff, 0x0, 0x0},
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.safe_lut_tbl = {0xfff0, 0x0, 0x0},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(qcm2290_qos_linear),
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.entries = qcm2290_qos_linear
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},
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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/*************************************************************
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* Hardware catalog
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*************************************************************/
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@@ -1915,29 +1832,7 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
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.mdss_irqs = IRQ_SM8250_MASK,
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};
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static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
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.caps = &qcm2290_dpu_caps,
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.ubwc = &qcm2290_ubwc_cfg,
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.mdp_count = ARRAY_SIZE(qcm2290_mdp),
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.mdp = qcm2290_mdp,
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.ctl_count = ARRAY_SIZE(qcm2290_ctl),
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.ctl = qcm2290_ctl,
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.sspp_count = ARRAY_SIZE(qcm2290_sspp),
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.sspp = qcm2290_sspp,
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.mixer_count = ARRAY_SIZE(qcm2290_lm),
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.mixer = qcm2290_lm,
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.dspp_count = ARRAY_SIZE(qcm2290_dspp),
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.dspp = qcm2290_dspp,
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.pingpong_count = ARRAY_SIZE(qcm2290_pp),
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.pingpong = qcm2290_pp,
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.intf_count = ARRAY_SIZE(qcm2290_intf),
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.intf = qcm2290_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.perf = &qcm2290_perf_data,
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.mdss_irqs = IRQ_SC7180_MASK,
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};
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#include "catalog/dpu_6_5_qcm2290.h"
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#include "catalog/dpu_6_3_sm6115.h"
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#include "catalog/dpu_7_0_sm8350.h"
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