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ARM: dts: Group omap3 CM_CLKSEL_PER clocks

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The clksel related registers on omap3 cause unique_unit_address and
node_name_chars_strict warnings with the W=1 or W=2 make flags enabled.

With the clock drivers updated, we can now avoid most of these warnings
by grouping the TI component clocks using the TI clksel binding, and
with the use of clock-output-names property to avoid non-standard node
names for the clocks.

Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
2022-04-29 09:57:36 +03:00
parent cab3db1b8d
commit c22a3d8cad
1 changed files with 68 additions and 60 deletions
Download Patch File Download Diff File Expand all files Collapse all files

128
arch/arm/boot/dts/omap3xxx-clocks.dtsi
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@@ -1338,11 +1338,75 @@ mcbsp4_gate_fck: clock-mcbsp4-gate-fck {
};
};
gpt2_mux_fck: gpt2_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
/* CM_CLKSEL_PER */
clock@1040 {
compatible = "ti,clksel";
reg = <0x1040>;
#clock-cells = <2>;
#address-cells = <0>;
gpt2_mux_fck: clock-gpt2-mux-fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt2_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
};
gpt3_mux_fck: clock-gpt3-mux-fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt3_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <1>;
};
gpt4_mux_fck: clock-gpt4-mux-fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt4_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <2>;
};
gpt5_mux_fck: clock-gpt5-mux-fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt5_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <3>;
};
gpt6_mux_fck: clock-gpt6-mux-fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt6_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <4>;
};
gpt7_mux_fck: clock-gpt7-mux-fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt7_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <5>;
};
gpt8_mux_fck: clock-gpt8-mux-fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt8_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <6>;
};
gpt9_mux_fck: clock-gpt9-mux-fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt9_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <7>;
};
};
gpt2_fck: gpt2_fck {
@@ -1351,98 +1415,42 @@ gpt2_fck: gpt2_fck {
clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
};
gpt3_mux_fck: gpt3_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <1>;
reg = <0x1040>;
};
gpt3_fck: gpt3_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
};
gpt4_mux_fck: gpt4_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <2>;
reg = <0x1040>;
};
gpt4_fck: gpt4_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
};
gpt5_mux_fck: gpt5_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <3>;
reg = <0x1040>;
};
gpt5_fck: gpt5_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
};
gpt6_mux_fck: gpt6_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <4>;
reg = <0x1040>;
};
gpt6_fck: gpt6_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
};
gpt7_mux_fck: gpt7_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <5>;
reg = <0x1040>;
};
gpt7_fck: gpt7_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
};
gpt8_mux_fck: gpt8_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <6>;
reg = <0x1040>;
};
gpt8_fck: gpt8_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
};
gpt9_mux_fck: gpt9_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <7>;
reg = <0x1040>;
};
gpt9_fck: gpt9_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";