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Revert "drm/amd/display: Correct hubp GfxVersion verification"

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This reverts commit 3303aa64e7 ("drm/amd/display: Correct hubp GfxVersion verification")

Reason for revert: Got blank screen issues while doing PNP

Reviewed-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Nicholas Carbones <Nicholas.Carbones@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Carbones
2026-02-09 11:34:00 +08:00
committed by Alex Deucher
parent 1a524d9a87
commit c1cf87eb79
3 changed files with 33 additions and 46 deletions
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31
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
View File

@@ -145,26 +145,21 @@ void hubp1_program_tiling(
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase);
ASSERT(info->gfxversion == DcGfxVersion9);
if (info->gfxversion == DcGfxVersion9) {
REG_UPDATE_6(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
NUM_BANKS, log_2(info->gfx9.num_banks),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
NUM_SE, log_2(info->gfx9.num_shader_engines),
NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
REG_UPDATE_4(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle,
META_LINEAR, info->gfx9.meta_linear,
RB_ALIGNED, info->gfx9.rb_aligned,
PIPE_ALIGNED, info->gfx9.pipe_aligned);
} else {
hubp1_clear_tiling(&hubp1->base);
}
REG_UPDATE_6(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
NUM_BANKS, log_2(info->gfx9.num_banks),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
NUM_SE, log_2(info->gfx9.num_shader_engines),
NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
REG_UPDATE_4(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle,
META_LINEAR, info->gfx9.meta_linear,
RB_ALIGNED, info->gfx9.rb_aligned,
PIPE_ALIGNED, info->gfx9.pipe_aligned);
}
void hubp1_program_size(

24
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
View File

@@ -313,22 +313,18 @@ static void hubp2_program_tiling(
const struct dc_tiling_info *info,
const enum surface_pixel_format pixel_format)
{
ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase);
ASSERT(info->gfxversion == DcGfxVersion9);
if (info->gfxversion == DcGfxVersion9) {
REG_UPDATE_3(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
REG_UPDATE_3(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
REG_UPDATE_4(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle,
META_LINEAR, 0,
RB_ALIGNED, 0,
PIPE_ALIGNED, 0);
} else {
hubp2_clear_tiling(&hubp2->base);
}
REG_UPDATE_4(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle,
META_LINEAR, 0,
RB_ALIGNED, 0,
PIPE_ALIGNED, 0);
}
void hubp2_program_size(

24
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
View File

@@ -321,22 +321,18 @@ void hubp3_program_tiling(
const struct dc_tiling_info *info,
const enum surface_pixel_format pixel_format)
{
ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase);
ASSERT(info->gfxversion == DcGfxVersion9);
if (info->gfxversion == DcGfxVersion9) {
REG_UPDATE_4(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags),
NUM_PKRS, log_2(info->gfx9.num_pkrs));
REG_UPDATE_4(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags),
NUM_PKRS, log_2(info->gfx9.num_pkrs));
REG_UPDATE_3(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle,
META_LINEAR, info->gfx9.meta_linear,
PIPE_ALIGNED, info->gfx9.pipe_aligned);
} else {
hubp3_clear_tiling(&hubp2->base);
}
REG_UPDATE_3(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle,
META_LINEAR, info->gfx9.meta_linear,
PIPE_ALIGNED, info->gfx9.pipe_aligned);
}