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ice: Add PHY OFFSET_READY register clearing

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Add a possibility to mark all transmitted/received timestamps as invalid
by clearing PHY OFFSET_READY registers.

Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Link: https://lore.kernel.org/r/20240528-next-2024-05-28-ptp-refactors-v1-4-c082739bb6f6@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Karol Kolacinski
2024-05-28 16:03:54 -07:00
committed by Jakub Kicinski
parent 0d80bbe254
commit c199b31a04
3 changed files with 42 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/net/ethernet/intel/ice/ice_ptp.c
View File

@@ -1933,11 +1933,14 @@ ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts)
struct ice_hw *hw = &pf->hw;
int err;
/* For Vernier mode, we need to recalibrate after new settime
* Start with disabling timestamp block
/* For Vernier mode on E82X, we need to recalibrate after new settime.
* Start with marking timestamps as invalid.
*/
if (pf->ptp.port.link_up)
ice_ptp_port_phy_stop(&pf->ptp.port);
if (hw->ptp.phy_model == ICE_PHY_E82X) {
err = ice_ptp_clear_phy_offset_ready_e82x(hw);
if (err)
dev_warn(ice_pf_to_dev(pf), "Failed to mark timestamps as invalid before settime\n");
}
if (!ice_ptp_lock(hw)) {
err = -EBUSY;

34
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
View File

@@ -2409,6 +2409,40 @@ int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port)
return 0;
}
/**
* ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers
* @hw: pointer to the HW struct
*
* Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted
* and received timestamps as invalid.
*
* Return: 0 on success, other error codes when failed to write to PHY
*/
int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw)
{
u8 port;
for (port = 0; port < hw->ptp.num_lports; port++) {
int err;
err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0);
if (err) {
dev_warn(ice_hw_to_dev(hw),
"Failed to clear PHY TX_OFFSET_READY register\n");
return err;
}
err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0);
if (err) {
dev_warn(ice_hw_to_dev(hw),
"Failed to clear PHY RX_OFFSET_READY register\n");
return err;
}
}
return 0;
}
/**
* ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time
* @hw: pointer to the HW struct

1
drivers/net/ethernet/intel/ice/ice_ptp_hw.h
View File

@@ -208,6 +208,7 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time);
int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw);
int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
void ice_ptp_reset_ts_memory(struct ice_hw *hw);