drm/amdgpu: enumerate UMSCH HW IP

This part enumerates a UMSCH block under hardware id (22) at version
2.2.0 rather than under VCN. Add the UMSCH hardware id, an IP enum
slot, and the discovery name/map entries so it is recognized. No IP
block is wired up yet; this only makes the IP discoverable.

The multimedia IP setup assumed VCN/VCE/UVD was always present; handle
the case where it is absent so init does not fail with -EINVAL.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ruijing Dong
2026-06-12 14:39:31 -04:00
committed by Alex Deucher
parent 6322d278a2
commit c18cd8d6e0
4 changed files with 12 additions and 2 deletions

View File

@@ -63,6 +63,7 @@ const char *hw_ip_names[MAX_HWIP] = {
[VCN1_HWIP] = "VCN1",
[VCE_HWIP] = "VCE",
[VPE_HWIP] = "VPE",
[UMSCH_HWIP] = "UMSCH",
[DF_HWIP] = "DF",
[DCE_HWIP] = "DCE",
[OSSSYS_HWIP] = "OSSSYS",

View File

@@ -247,6 +247,7 @@ static const char *hw_id_names[HW_ID_MAX] = {
[XGBE_HWID] = "XGBE",
[MP0_HWID] = "MP0",
[VPE_HWID] = "VPE",
[UMSCH_HWID] = "UMSCH",
[ATU_HWID] = "ATU",
[AIGC_HWID] = "AIGC",
};
@@ -279,6 +280,7 @@ static int hw_id_map[MAX_HWIP] = {
[DCI_HWIP] = DCI_HWID,
[PCIE_HWIP] = PCIE_HWID,
[VPE_HWIP] = VPE_HWID,
[UMSCH_HWIP] = UMSCH_HWID,
[ISP_HWIP] = ISP_HWID,
[ATU_HWIP] = ATU_HWID,
};
@@ -2845,7 +2847,12 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
return -EINVAL;
}
} else {
switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
uint32_t vcn_version = amdgpu_ip_version(adev, UVD_HWIP, 0);
/* no VCN discovered; nothing to add */
if (!vcn_version)
return 0;
switch (vcn_version) {
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
@@ -2913,7 +2920,7 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
default:
dev_err(adev->dev,
"Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
amdgpu_ip_version(adev, UVD_HWIP, 0));
vcn_version);
return -EINVAL;
}
}

View File

@@ -68,6 +68,7 @@ enum amd_hw_ip_block_type {
ISP_HWIP,
ATU_HWIP,
AIGC_HWIP,
UMSCH_HWIP,
MAX_HWIP
};

View File

@@ -44,6 +44,7 @@
#define SDPMUX_HWID 19
#define NTB_HWID 20
#define VPE_HWID 21
#define UMSCH_HWID 22
#define IOHC_HWID 24
#define L2IMU_HWID 28
#define VCE_HWID 32