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drm/amd/display: Clear pipe pointers on pipe reset

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[Why]
We want to clean up unnecessary asserts, one of which is an assert in
resource_is_pipe_type that fires if a pipe has no stream and still has
pointers to other pipes ("dangling state"). This gets hit because pipes
are not properly cleaned up in reset_back_end_for_pipe. When resetting a
pipe, the existing MPCC / ODM combine pointers are no longer valid,
especially when we put ODM in bypass.

[How]
 - reset pipe pointers in reset_back_end_for_pipe
 - remove useless code to avoid confusion
     (a long time ago it had a reason to be there, not anymore)

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Joshua Aberback
2024-10-03 17:28:11 -04:00
committed by Alex Deucher
parent c6335dad37
commit c0933f1de2
2 changed files with 8 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
View File

@@ -2766,7 +2766,6 @@ void dcn20_reset_back_end_for_pipe(
struct pipe_ctx *pipe_ctx,
struct dc_state *context)
{
int i;
struct dc_link *link = pipe_ctx->stream->link;
const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
@@ -2833,19 +2832,16 @@ void dcn20_reset_back_end_for_pipe(
}
}
for (i = 0; i < dc->res_pool->pipe_count; i++)
if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
break;
if (i == dc->res_pool->pipe_count)
return;
/*
* In case of a dangling plane, setting this to NULL unconditionally
* causes failures during reset hw ctx where, if stream is NULL,
* it is expected that the pipe_ctx pointers to pipes and plane are NULL.
*/
pipe_ctx->stream = NULL;
pipe_ctx->top_pipe = NULL;
pipe_ctx->bottom_pipe = NULL;
pipe_ctx->next_odm_pipe = NULL;
pipe_ctx->prev_odm_pipe = NULL;
DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
}

12
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
View File

@@ -1883,7 +1883,6 @@ void dcn401_reset_back_end_for_pipe(
struct pipe_ctx *pipe_ctx,
struct dc_state *context)
{
int i;
struct dc_link *link = pipe_ctx->stream->link;
const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
@@ -1954,19 +1953,16 @@ void dcn401_reset_back_end_for_pipe(
dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, REFCLK, pipe_ctx->stream_res.tg->inst);
}
for (i = 0; i < dc->res_pool->pipe_count; i++)
if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
break;
if (i == dc->res_pool->pipe_count)
return;
/*
* In case of a dangling plane, setting this to NULL unconditionally
* causes failures during reset hw ctx where, if stream is NULL,
* it is expected that the pipe_ctx pointers to pipes and plane are NULL.
*/
pipe_ctx->stream = NULL;
pipe_ctx->top_pipe = NULL;
pipe_ctx->bottom_pipe = NULL;
pipe_ctx->next_odm_pipe = NULL;
pipe_ctx->prev_odm_pipe = NULL;
DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
}