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KVM: x86: Inhibit code #DBs in MOV-SS shadow for all Intel compat vCPUs
Treat code #DBs as inhibited in MOV/POP-SS shadows for vCPU models that
are Intel compatible, not just strictly vCPUs with vendor==Intel. The
behavior is explicitly called out in the SDM, and thus architectural, i.e.
applies to all CPUs that implement Intel's architecture, and isn't a quirk
that is unique to CPUs manufactured by Intel:
However, if an instruction breakpoint is placed on an instruction located
immediately after a POP SS/MOV SS instruction, the breakpoint will be
suppressed as if EFLAGS.RF were 1.
Applying the behavior strictly to Intel wasn't intentional, KVM simply
didn't have a concept of "Intel compatible" as of commit baf67ca8e5
("KVM: x86: Suppress code #DBs on Intel if MOV/POP SS blocking is active").
Link: https://lore.kernel.org/r/20240405235603.1173076-6-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
This commit is contained in:
@@ -9028,19 +9028,17 @@ EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
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static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu)
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{
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u32 shadow;
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if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF)
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return true;
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/*
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* Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active,
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* but AMD CPUs do not. MOV/POP SS blocking is rare, check that first
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* to avoid the relatively expensive CPUID lookup.
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* Intel compatible CPUs inhibit code #DBs when MOV/POP SS blocking is
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* active, but AMD compatible CPUs do not.
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*/
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shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
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return (shadow & KVM_X86_SHADOW_INT_MOV_SS) &&
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guest_cpuid_is_intel(vcpu);
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if (!guest_cpuid_is_intel_compatible(vcpu))
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return false;
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return static_call(kvm_x86_get_interrupt_shadow)(vcpu) & KVM_X86_SHADOW_INT_MOV_SS;
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}
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static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu,
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