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arm64: dts: ti: k3-j784s4-evm: Enable USB3 support

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The board uses SERDES0 Lane 3 for USB3 IP. So update the
SerDes lane info for USB. Add the pin mux data and
enable USB3 support.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # k3-j784s4-evm
Link: https://lore.kernel.org/r/20240507095545.8210-3-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Matt Ranostay
2024-05-07 15:25:45 +05:30
committed by Vignesh Raghavendra
parent 75843b6374
commit bed97e94ee
1 changed files with 41 additions and 0 deletions
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41
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
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@@ -415,6 +415,13 @@ J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */
J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */
>;
};
main_usbss0_pins_default: main-usbss0-default-pins {
bootph-all;
pinctrl-single,pins = <
J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */
>;
};
};
&wkup_pmx2 {
@@ -1171,6 +1178,40 @@ &dss {
<&k3_clks 218 22>;
};
&serdes0 {
status = "okay";
serdes0_usb_link: phy@3 {
reg = <3>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz0 4>;
};
};
&serdes_wiz0 {
status = "okay";
};
&usb_serdes_mux {
idle-states = <0>; /* USB0 to SERDES lane 3 */
};
&usbss0 {
status = "okay";
pinctrl-0 = <&main_usbss0_pins_default>;
pinctrl-names = "default";
ti,vbus-divider;
};
&usb0 {
dr_mode = "otg";
maximum-speed = "super-speed";
phys = <&serdes0_usb_link>;
phy-names = "cdns3,usb3-phy";
};
&serdes_wiz4 {
status = "okay";
};