mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-07-22 02:17:36 -04:00
Code Issues Packages Projects Releases Wiki Activity

tools/x86/kcpuid: Update bitfields to x86-cpuid-db v3.1

Browse Source 
Update kcpuid's CSV file to version 3.1, as generated by x86-cpuid-db.

Summary of the v3.1 changes:

* Fix a few typos that were found during the kernel CPUID data model
  review. Also include fixes found using an LLM agent review.

* Rename thrd_director_nclasses to hw_feedback_nclasses as it's the
  name used in Intel SDM.

See https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v3.1/CHANGELOG.rst
for more info.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://patch.msgid.link/cbe9ff395b3269e112ff7ca414d726ffd7bf0787.1780506200.git.m.wieczorretman@pm.me
This commit is contained in:
Maciej Wieczor-Retman
2026-06-03 17:10:49 +00:00
committed by Borislav Petkov (AMD)
parent 111cbb4596
commit bdf4d82806
1 changed files with 26 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

52
tools/arch/x86/kcpuid/cpuid.csv
View File

@@ -1,5 +1,5 @@
# SPDX-License-Identifier: CC0-1.0
# Generator: x86-cpuid-db v3.0
# Generator: x86-cpuid-db v3.1
#
# Auto-generated file.
@@ -177,7 +177,7 @@
0x6, 0, ebx, 3:0, n_therm_thresholds , Digital thermometer thresholds
0x6, 0, ecx, 0, aperfmperf , MPERF/APERF MSRs (effective frequency interface)
0x6, 0, ecx, 3, epb , IA32_ENERGY_PERF_BIAS MSR
0x6, 0, ecx, 15:8, thrd_director_nclasses , Number of classes, Intel thread director
0x6, 0, ecx, 15:8, hw_feedback_nclasses , Number of Intel Thread Director classes
0x6, 0, edx, 0, perfcap_reporting , Performance capability reporting
0x6, 0, edx, 1, encap_reporting , Energy efficiency capability reporting
0x6, 0, edx, 11:8, feedback_sz , Feedback interface structure size, in 4K pages
@@ -247,10 +247,10 @@
0x7, 0, edx, 1, sgx_keys , Intel SGX attestation services
0x7, 0, edx, 2, avx512_4vnniw , AVX-512 neural network instructions
0x7, 0, edx, 3, avx512_4fmaps , AVX-512 multiply accumulation single precision
0x7, 0, edx, 4, fsrm , Fast short REP MOV
0x7, 0, edx, 4, fsrm , Fast short REP MOVSB
0x7, 0, edx, 5, uintr , User interrupts
0x7, 0, edx, 8, avx512_vp2intersect , VP2INTERSECT{D,Q} instructions
0x7, 0, edx, 9, srdbs_ctrl , SRBDS mitigation MSR
0x7, 0, edx, 9, srbds_ctrl , SRBDS mitigation MSR
0x7, 0, edx, 10, md_clear , VERW MD_CLEAR microcode
0x7, 0, edx, 11, rtm_always_abort , XBEGIN (RTM transaction) always aborts
0x7, 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit
@@ -296,8 +296,8 @@
0x7, 2, edx, 0, intel_psfd , Intel predictive store forward disable
0x7, 2, edx, 1, ipred_ctrl , MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}
0x7, 2, edx, 2, rrsba_ctrl , MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}
0x7, 2, edx, 3, ddp_ctrl , MSR bit IA32_SPEC_CTRL.DDPD_U
0x7, 2, edx, 4, bhi_ctrl , MSR bit IA32_SPEC_CTRL.BHI_DIS_S
0x7, 2, edx, 3, ddp_ctrl , MSR bit IA32_SPEC_CTRL.DDPD_U
0x7, 2, edx, 4, bhi_ctrl , MSR bit IA32_SPEC_CTRL.BHI_DIS_S
0x7, 2, edx, 5, mcdt_no , MCDT mitigation not needed
0x7, 2, edx, 6, uclock_disable , UC-lock disable
@@ -368,7 +368,7 @@
0xd, 1, ecx, 8, xss_pt , PT state
0xd, 1, ecx, 10, xss_pasid , PASID state
0xd, 1, ecx, 11, xss_cet_u , CET user state
0xd, 1, ecx, 12, xss_cet_p , CET supervisor state
0xd, 1, ecx, 12, xss_cet_s , CET supervisor state
0xd, 1, ecx, 13, xss_hdc , HDC state
0xd, 1, ecx, 14, xss_uintr , UINTR state
0xd, 1, ecx, 15, xss_lbr , LBR state
@@ -433,7 +433,7 @@
0x12, 1, eax, 7, secs_attr_kss , Key Separation and Sharing
0x12, 1, eax, 10, secs_attr_aexnotify , Enclave threads: AEX notifications
0x12, 1, ecx, 0, xfrm_x87 , Enclave XFRM.X87
0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SEE
0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SSE
0x12, 1, ecx, 2, xfrm_avx , Enclave XFRM.AVX
0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave XFRM.BNDREGS (MPX BND0-BND3 registers)
0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave XFRM.BNDCSR (MPX BNDCFGU/BNDSTATUS registers)
@@ -466,9 +466,9 @@
0x14, 0, ecx, 0, topa_output , ToPA output scheme
0x14, 0, ecx, 1, topa_multiple_entries , ToPA tables can hold multiple entries
0x14, 0, ecx, 2, single_range_output , Single-range output
0x14, 0, ecx, 3, trance_transport_output, Trace Transport subsystem output
0x14, 0, ecx, 3, trace_transport_output , Trace Transport subsystem output
0x14, 0, ecx, 31, ip_payloads_lip , IP payloads have LIP values (CS base included)
0x14, 1, eax, 2:0, num_address_ranges , Number of configurable Address Ranges
0x14, 1, eax, 2:0, num_address_ranges , Number of configurable address ranges
0x14, 1, eax, 31:16, mtc_periods_bmp , MTC period encodings bitmap
0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Cycle Threshold encodings bitmap
0x14, 1, ebx, 31:16, psb_periods_bmp , Configurable PSB frequency encodings bitmap
@@ -494,7 +494,7 @@
0x17, 0, ebx, 15:0, soc_vendor_id , SoC vendor ID
0x17, 0, ebx, 16, is_vendor_scheme , Assigned by industry enumeration scheme (not Intel)
0x17, 0, ecx, 31:0, soc_proj_id , SoC project ID, assigned by vendor
0x17, 0, edx, 31:0, soc_stepping_id , Soc project stepping ID, assigned by vendor
0x17, 0, edx, 31:0, soc_stepping_id , SoC project stepping ID, assigned by vendor
0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor Brand ID string, bytes subleaf_nr * (0 -> 3)
0x17, 3:1, ebx, 31:0, vendor_brand_b , Vendor Brand ID string, bytes subleaf_nr * (4 -> 7)
0x17, 3:1, ecx, 31:0, vendor_brand_c , Vendor Brand ID string, bytes subleaf_nr * (8 -> 11)
@@ -514,12 +514,12 @@
0x18, 31:0, edx, 4:0, tlb_type , Translation cache type (TLB type)
0x18, 31:0, edx, 7:5, tlb_cache_level , Translation cache level (1-based)
0x18, 31:0, edx, 8, is_fully_associative , Fully-associative
0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max number of addressable IDs - 1
0x18, 31:0, edx, 25:14, tlb_max_addressable_ids, Max number of addressable IDs - 1
# Leaf 19H
# Intel key locker
0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key Locker restriction
0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key locker restriction
0x19, 0, eax, 1, kl_no_encrypt , No-encrypt key locker restriction
0x19, 0, eax, 2, kl_no_decrypt , No-decrypt key locker restriction
0x19, 0, ebx, 0, aes_keylocker , AES key locker instructions
@@ -546,7 +546,7 @@
# Intel LBR (Last Branch Record)
0x1c, 0, eax, 7:0, lbr_depth_mask , Max LBR stack depth bitmask
0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs maybe cleared on MWAIT C-state > C1
0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs may be cleared on MWAIT C-state > C1
0x1c, 0, eax, 31, lbr_ip_is_lip , LBR IP contain Last IP (otherwise effective IP)
0x1c, 0, ebx, 0, lbr_cpl , CPL filtering
0x1c, 0, ebx, 1, lbr_branch_filter , Branch filtering
@@ -591,8 +591,8 @@
# Intel TD (Trust Domain)
0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vendor ID string bytes 0 - 3
0x21, 0, ecx, 31:0, tdx_vendorid_2 , CPU vendor ID string bytes 8 - 11
0x21, 0, edx, 31:0, tdx_vendorid_1 , CPU vendor ID string bytes 4 - 7
0x21, 0, ecx, 31:0, tdx_vendorid_2 , TDX vendor ID string bytes 8 - 11
0x21, 0, edx, 31:0, tdx_vendorid_1 , TDX vendor ID string bytes 4 - 7
# Leaf 23H
# Intel Architectural Performance Monitoring Extended (ArchPerfmonExt)
@@ -857,7 +857,7 @@
0x8000000a, 0, edx, 1, lbrv , LBR virtualization
0x8000000a, 0, edx, 2, svm_lock , SVM lock
0x8000000a, 0, edx, 3, nrip_save , NRIP save support on #VMEXIT
0x8000000a, 0, edx, 4, tsc_scale , MSR based TSC rate control
0x8000000a, 0, edx, 4, tsc_scale , MSR-based TSC rate control
0x8000000a, 0, edx, 5, vmcb_clean , VMCB clean bits support
0x8000000a, 0, edx, 6, flushbyasid , Flush by ASID + Extended VMCB TLB_Control
0x8000000a, 0, edx, 7, decodeassists , Decode Assists support
@@ -895,7 +895,7 @@
0x8000001a, 0, eax, 0, fp_128 , Internal FP/SIMD exec data path is 128-bits wide
0x8000001a, 0, eax, 1, movu_preferred , SSE: MOVU* better than MOVL*/MOVH*
0x8000001a, 0, eax, 2, fp_256 , internal FP/SSE exec data path is 256-bits wide
0x8000001a, 0, eax, 2, fp_256 , Internal FP/SSE exec data path is 256-bits wide
# Leaf 8000001BH
# AMD IBS (Instruction-Based Sampling)
@@ -917,7 +917,7 @@
# AMD LWP (Lightweight Profiling)
0x8000001c, 0, eax, 0, os_lwp_avail , OS: LWP is available to application programs
0x8000001c, 0, eax, 1, os_lpwval , OS: LWPVAL instruction
0x8000001c, 0, eax, 1, os_lwpval , OS: LWPVAL instruction
0x8000001c, 0, eax, 2, os_lwp_ire , OS: Instructions Retired Event
0x8000001c, 0, eax, 3, os_lwp_bre , OS: Branch Retired Event
0x8000001c, 0, eax, 4, os_lwp_dme , OS: Dcache Miss Event
@@ -934,13 +934,13 @@
0x8000001c, 0, ecx, 5, lwp_data_addr , Cache miss events report data cache address
0x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Cache latency rounding amount
0x8000001c, 0, ecx, 15:9, lwp_version , LWP version
0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP event ring buffer min size, 32 event records units
0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP event ring buffer min size, 32 event record units
0x8000001c, 0, ecx, 28, lwp_branch_predict , Branches Retired events can be filtered
0x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filtering (IPI, IPF, BaseIP, and LimitIP @ LWPCP)
0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-related events: filter by cache level
0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-related events: filter by latency
0x8000001c, 0, edx, 0, hw_lwp_avail , HW: LWP available
0x8000001c, 0, edx, 1, hw_lpwval , HW: LWPVAL available
0x8000001c, 0, edx, 1, hw_lwpval , HW: LWPVAL available
0x8000001c, 0, edx, 2, hw_lwp_ire , HW: Instructions Retired Event
0x8000001c, 0, edx, 3, hw_lwp_bre , HW: Branch Retired Event
0x8000001c, 0, edx, 4, hw_lwp_dme , HW: Dcache Miss Event
@@ -1040,8 +1040,8 @@
0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR Upper Address Ignore
0x80000021, 0, eax, 8, autoibrs , EFER MSR Automatic IBRS
0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL MSR not available
0x80000021, 0, eax, 10, fsrs , Fast Short Rep STOSB
0x80000021, 0, eax, 11, fsrc , Fast Short Rep CMPSB
0x80000021, 0, eax, 10, fsrs , Fast Short REP STOSB
0x80000021, 0, eax, 11, fsrc , Fast Short REP CMPSB
0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch control MSR
0x80000021, 0, eax, 16, opcode_reclaim , Reserves opcode space
0x80000021, 0, eax, 17, user_cpuid_disable , #GP when executing CPUID at CPL > 0
@@ -1093,9 +1093,9 @@
# Maximum Transmeta leaf + CPU vendor string
0x80860000, 0, eax, 31:0, max_tra_leaf , Maximum Transmeta leaf
0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmeta Vendor ID string bytes 0 - 3
0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmeta Vendor ID string bytes 8 - 11
0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmeta Vendor ID string bytes 4 - 7
0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmeta vendor ID string bytes 0 - 3
0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmeta vendor ID string bytes 8 - 11
0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmeta vendor ID string bytes 4 - 7
# Leaf 80860001H
# Transmeta extended CPU features
1 # SPDX-License-Identifier: CC0-1.0
2 # Generator: x86-cpuid-db v3.0 # Generator: x86-cpuid-db v3.1
3 #
4 # Auto-generated file.
5 # Please submit all updates and bugfixes to https://x86-cpuid.org
177 0x7, 0, ebx, 3, bmi1 , Bit manipulation extensions group 1
178 0x7, 0, ebx, 4, hle , Hardware Lock Elision
179 0x7, 0, ebx, 5, avx2 , AVX2 instruction set
180 0x7, 0, ebx, 6, fdp_excptn_only , FPU Data Pointer updated only on x87 exceptions
181 0x7, 0, ebx, 7, smep , Supervisor Mode Execution Protection
182 0x7, 0, ebx, 8, bmi2 , Bit manipulation extensions group 2
183 0x7, 0, ebx, 9, erms , Enhanced REP MOVSB/STOSB
247 0x7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16
248 0x7, 0, edx, 23, avx512_fp16 , AVX-512 FP16 instructions
249 0x7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture
250 0x7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer
251 0x7, 0, edx, 26, spec_ctrl , Speculation Control (IBRS/IBPB: indirect branch restrictions)
252 0x7, 0, edx, 27, intel_stibp , Single thread indirect branch predictors
253 0x7, 0, edx, 28, flush_l1d , FLUSH L1D cache: IA32_FLUSH_CMD MSR
254 0x7, 0, edx, 29, arch_capabilities , Intel IA32_ARCH_CAPABILITIES MSR
255 0x7, 0, edx, 30, core_capabilities , IA32_CORE_CAPABILITIES MSR
256 0x7, 0, edx, 31, spec_ctrl_ssbd , Speculative store bypass disable
296 0xa, 0, ebx, 0, no_core_cycle , Core cycle event not available
297 0xa, 0, ebx, 1, no_instruction_retired , Instruction retired event not available
298 0xa, 0, ebx, 2, no_reference_cycles , Reference cycles event not available
299 0xa, 0, ebx, 3, no_llc_reference , LLC-reference event not available
300 0xa, 0, ebx, 4, no_llc_misses , LLC-misses event not available
301 0xa, 0, ebx, 5, no_br_insn_retired , Branch instruction retired event not available
302 0xa, 0, ebx, 6, no_br_misses_retired , Branch mispredict retired event not available
303 0xa, 0, ebx, 7, no_topdown_slots , Topdown slots event not available
368 0xf, 1, edx, 2, cqm_mbm_local , L3 QoS local bandwidth monitoring
369 # Leaf 10H
370 # Intel RDT / AMD PQoS allocation
371 0x10, 0, ebx, 1, cat_l3 , L3 Cache Allocation Technology
372 0x10, 0, ebx, 2, cat_l2 , L2 Cache Allocation Technology
373 0x10, 0, ebx, 3, mba , Memory Bandwidth Allocation
374 0x10, 2:1, eax, 4:0, cat_cbm_len , L3/L2_CAT capacity bitmask length, minus-one notation
433 0x14, 0, ebx, 8, tnt_disable , TNT packet generation disable
434 0x14, 0, ecx, 0, topa_output , ToPA output scheme
435 0x14, 0, ecx, 1, topa_multiple_entries , ToPA tables can hold multiple entries
436 0x14, 0, ecx, 2, single_range_output , Single-range output
437 0x14, 0, ecx, 3, trance_transport_output, Trace Transport subsystem output 0x14, 0, ecx, 3, trace_transport_output , Trace Transport subsystem output
438 0x14, 0, ecx, 31, ip_payloads_lip , IP payloads have LIP values (CS base included)
439 0x14, 1, eax, 2:0, num_address_ranges , Number of configurable Address Ranges 0x14, 1, eax, 2:0, num_address_ranges , Number of configurable address ranges
466 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Maximum leaf 0x18 subleaf
467 0x18, 31:0, ebx, 0, tlb_4k_page , TLB supports 4KB-page entries
468 0x18, 31:0, ebx, 1, tlb_2m_page , TLB supports 2MB-page entries
469 0x18, 31:0, ebx, 2, tlb_4m_page , TLB supports 4MB-page entries
470 0x18, 31:0, ebx, 3, tlb_1g_page , TLB supports 1GB-page entries
471 0x18, 31:0, ebx, 10:8, hard_partitioning , Partitioning between logical CPUs
472 0x18, 31:0, ebx, 31:16, n_way_associative , Ways of associativity
473 0x18, 31:0, ecx, 31:0, n_sets , Number of sets
474 0x18, 31:0, edx, 4:0, tlb_type , Translation cache type (TLB type)
494 0x1b, 31:0, eax, 11:0, pconfig_subleaf_type , CPUID 0x1b subleaf type
495 0x1b, 31:0, ebx, 31:0, pconfig_target_id_x , A supported PCONFIG target ID
496 0x1b, 31:0, ecx, 31:0, pconfig_target_id_y , A supported PCONFIG target ID
497 0x1b, 31:0, edx, 31:0, pconfig_target_id_z , A supported PCONFIG target ID
498 # Leaf 1CH
499 # Intel LBR (Last Branch Record)
500 0x1c, 0, eax, 7:0, lbr_depth_mask , Max LBR stack depth bitmask
514 0x1d, 1, eax, 31:16, amx_tile_size , AMX single tile's size, in bytes
515 0x1d, 1, ebx, 15:0, amx_tile_row_size , AMX tile single row's size, in bytes
516 0x1d, 1, ebx, 31:16, amx_palette_nr_tiles , AMX palette number of tiles
517 0x1d, 1, ecx, 15:0, amx_tile_nr_rows , AMX tile max number of rows
518 # Leaf 1EH
519 # Intel TMUL (Tile-matrix Multiply)
520 0x1e, 0, ebx, 7:0, tmul_maxk , TMUL unit maximum height, K (rows or columns)
521 0x1e, 0, ebx, 23:8, tmul_maxn , TMUL unit maximum SIMD dimension, N (column bytes)
522 # Leaf 1FH
523 # Intel extended topology v2
524 0x1f, 5:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive)
525 0x1f, 5:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances of this domain
546 0x23, 0, ebx, 0, unitmask2 , IA32_PERFEVTSELx MSRs UnitMask2 bit
547 0x23, 0, ebx, 1, eq , IA32_PERFEVTSELx MSRs EQ bit
548 0x23, 0, ebx, 2, rdpmc_user_disable , RDPMC userspace disable
549 0x23, 1, eax, 31:0, gp_counters , Bitmap of general-purpose PMU counters
550 0x23, 1, ebx, 31:0, fixed_counters , Bitmap of fixed PMU counters
551 0x23, 2, eax, 31:0, acr_gp_reload , Bitmap of general-purpose counters that can be reloaded
552 0x23, 2, ebx, 31:0, acr_fixed_reload , Bitmap of fixed counters that can be reloaded
591 # Leaf 80000001H
592 # Extended CPU features
593 0x80000001, 0, eax, 3:0, e_stepping_id , Stepping ID
594 0x80000001, 0, eax, 7:4, e_base_model , Base processor model
595 0x80000001, 0, eax, 11:8, e_base_family , Base processor family
596 0x80000001, 0, eax, 13:12, e_base_type , Base processor type (Transmeta)
597 0x80000001, 0, eax, 19:16, e_ext_model , Extended processor model
598 0x80000001, 0, eax, 27:20, e_ext_family , Extended processor family
857 0x8000001c, 0, edx, 5, hw_lwp_cnh , HW: Clocks Not Halted event
858 0x8000001c, 0, edx, 6, hw_lwp_rnh , HW: Reference clocks Not Halted event
859 0x8000001c, 0, edx, 29, hw_lwp_cont , HW: LWP sampling in continuous mode
860 0x8000001c, 0, edx, 30, hw_lwp_ptsc , HW: Performance Time Stamp Counter in event records
861 0x8000001c, 0, edx, 31, hw_lwp_int , HW: Interrupt on threshold overflow
862 # Leaf 8000001DH
863 # AMD deterministic cache parameters
895 0x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV guest mandates 64-bit hypervisor
896 0x8000001f, 0, eax, 12, restricted_injection , Restricted Injection supported
897 0x8000001f, 0, eax, 13, alternate_injection , Alternate Injection supported
898 0x8000001f, 0, eax, 14, debug_swap , SEV-ES: Full debug state swap
899 0x8000001f, 0, eax, 15, disallow_host_ibs , SEV-ES: Disallowing IBS use by the host
900 0x8000001f, 0, eax, 16, virt_transparent_enc , Virtual Transparent Encryption
901 0x8000001f, 0, eax, 17, vmgexit_parameter , SEV_FEATURES: VmgexitParameter
917 0x80000020, 0, ebx, 3, bmec , Bandwidth Monitoring Event Configuration support
918 0x80000020, 0, ebx, 4, l3rr , L3 Range Reservation support
919 0x80000020, 0, ebx, 5, abmc , Assignable Bandwidth Monitoring Counters
920 0x80000020, 0, ebx, 6, sdciae , Smart Data Cache Injection (SDCI) Allocation Enforcement
921 0x80000020, 1, eax, 31:0, mba_limit_len , MBA enforcement limit size
922 0x80000020, 1, edx, 31:0, mba_cos_max , MBA max Class of Service number (zero-based)
923 0x80000020, 2, eax, 31:0, smba_limit_len , SMBA enforcement limit size
934 # AMD extended CPU features 2
935 0x80000021, 0, eax, 0, no_nested_data_bp , No nested data breakpoints
936 0x80000021, 0, eax, 1, fsgs_non_serializing , WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing
937 0x80000021, 0, eax, 2, lfence_rdtsc , LFENCE always serializing / synchronizes RDTSC
938 0x80000021, 0, eax, 3, smm_page_cfg_lock , SMM paging configuration lock
939 0x80000021, 0, eax, 6, null_sel_clr_base , Null selector clears base
940 0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR Upper Address Ignore
941 0x80000021, 0, eax, 8, autoibrs , EFER MSR Automatic IBRS
942 0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL MSR not available
943 0x80000021, 0, eax, 10, fsrs , Fast Short Rep STOSB 0x80000021, 0, eax, 10, fsrs , Fast Short REP STOSB
944 0x80000021, 0, eax, 11, fsrc , Fast Short Rep CMPSB 0x80000021, 0, eax, 11, fsrc , Fast Short REP CMPSB
945 0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch control MSR
946 0x80000021, 0, eax, 16, opcode_reclaim , Reserves opcode space
1040 0x80860007, 0, ebx, 31:0, cpu_cur_voltage , Current CPU voltage, in millivolts
1041 0x80860007, 0, ecx, 31:0, cpu_cur_perf_pctg , Current CPU performance percentage, 0 - 100
1042 0x80860007, 0, edx, 31:0, cpu_cur_gate_delay , Current CPU gate delay, in femtoseconds
1043 # Leaf C0000000H
1044 # Maximum Centaur/Zhaoxin leaf
1045 0xc0000000, 0, eax, 31:0, max_cntr_leaf , Maximum Centaur/Zhaoxin leaf
1046 # Leaf C0000001H
1047 # Centaur/Zhaoxin extended CPU features
1093
1094
1095
1096
1097
1098
1099
1100
1101