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drm/amd/pm: Add PMFW headers for SMU 13.0.6
Initial version of PMFW interface and message headers for SMU 13.0.6 support. v2: squash in location fixes (Alex) v3: squash in updates (Alex) Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar
@@ -0,0 +1,141 @@
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/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU_13_0_6_DRIVER_IF_H
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#define SMU_13_0_6_DRIVER_IF_H
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// *** IMPORTANT ***
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// PMFW TEAM: Always increment the interface version if
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// anything is changed in this file
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#define SMU13_0_6_DRIVER_IF_VERSION 0x08042022
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//I2C Interface
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#define NUM_I2C_CONTROLLERS 8
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#define I2C_CONTROLLER_ENABLED 1
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#define I2C_CONTROLLER_DISABLED 0
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#define MAX_SW_I2C_COMMANDS 24
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typedef enum {
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I2C_CONTROLLER_PORT_0, //CKSVII2C0
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I2C_CONTROLLER_PORT_1, //CKSVII2C1
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I2C_CONTROLLER_PORT_COUNT,
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} I2cControllerPort_e;
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typedef enum {
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UNSUPPORTED_1, //50 Kbits/s not supported anymore!
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I2C_SPEED_STANDARD_100K, //100 Kbits/s
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I2C_SPEED_FAST_400K, //400 Kbits/s
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I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode)
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UNSUPPORTED_2, //1 Mbits/s (in high speed mode) not supported anymore!
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UNSUPPORTED_3, //2.3 Mbits/s not supported anymore!
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I2C_SPEED_COUNT,
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} I2cSpeed_e;
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typedef enum {
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I2C_CMD_READ,
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I2C_CMD_WRITE,
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I2C_CMD_COUNT,
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} I2cCmdType_e;
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#define CMDCONFIG_STOP_BIT 0
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#define CMDCONFIG_RESTART_BIT 1
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#define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write
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#define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT)
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#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT)
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#define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT)
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typedef struct {
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uint8_t ReadWriteData; //Return data for read. Data to send for write
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uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write
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} SwI2cCmd_t; //SW I2C Command Table
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typedef struct {
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uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)
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uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select
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uint8_t SlaveAddress; //Slave address of device
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uint8_t NumCmds; //Number of commands
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SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS];
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} SwI2cRequest_t; // SW I2C Request Table
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typedef struct {
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SwI2cRequest_t SwI2cRequest;
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uint32_t Spare[8];
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uint32_t MmHubPadding[8]; // SMU internal use
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} SwI2cRequestExternal_t;
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typedef enum {
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PPCLK_VCLK,
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PPCLK_DCLK,
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PPCLK_SOCCLK,
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PPCLK_UCLK,
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PPCLK_FCLK,
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PPCLK_LCLK,
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PPCLK_COUNT,
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} PPCLK_e;
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typedef enum {
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GPIO_INT_POLARITY_ACTIVE_LOW,
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GPIO_INT_POLARITY_ACTIVE_HIGH,
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} GpioIntPolarity_e;
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//TODO confirm if this is used in SMU_13_0_6 PPSMC_MSG_SetUclkDpmMode
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typedef enum {
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UCLK_DPM_MODE_BANDWIDTH,
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UCLK_DPM_MODE_LATENCY,
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} UCLK_DPM_MODE_e;
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typedef struct {
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//0-26 SOC, 27-29 SOCIO
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uint16_t avgPsmCount[30];
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uint16_t minPsmCount[30];
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float avgPsmVoltage[30];
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float minPsmVoltage[30];
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} AvfsDebugTableAid_t;
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typedef struct {
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//0-27 GFX, 28-29 SOC
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uint16_t avgPsmCount[30];
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uint16_t minPsmCount[30];
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float avgPsmVoltage[30];
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float minPsmVoltage[30];
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} AvfsDebugTableXcd_t;
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// These defines are used with the following messages:
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// SMC_MSG_TransferTableDram2Smu
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// SMC_MSG_TransferTableSmu2Dram
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// #define TABLE_PPTABLE 0
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// #define TABLE_AVFS_PSM_DEBUG 1
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// #define TABLE_AVFS_FUSE_OVERRIDE 2
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// #define TABLE_PMSTATUSLOG 3
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// #define TABLE_SMU_METRICS 4
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// #define TABLE_DRIVER_SMU_CONFIG 5
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// #define TABLE_I2C_COMMANDS 6
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// #define TABLE_COUNT 7
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// // Table transfer status
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// #define TABLE_TRANSFER_OK 0x0
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// #define TABLE_TRANSFER_FAILED 0xFF
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// #define TABLE_TRANSFER_PENDING 0xAB
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#endif
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212
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
Normal file
212
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
Normal file
@@ -0,0 +1,212 @@
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/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU_13_0_6_PMFW_H
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#define SMU_13_0_6_PMFW_H
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#define NUM_VCLK_DPM_LEVELS 4
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#define NUM_DCLK_DPM_LEVELS 4
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#define NUM_SOCCLK_DPM_LEVELS 4
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#define NUM_LCLK_DPM_LEVELS 4
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#define NUM_UCLK_DPM_LEVELS 4
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#define NUM_FCLK_DPM_LEVELS 4
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#define NUM_XGMI_DPM_LEVELS 2
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#define NUM_CXL_BITRATES 4
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#define NUM_PCIE_BITRATES 4
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#define NUM_XGMI_BITRATES 4
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#define NUM_XGMI_WIDTHS 3
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typedef enum {
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/*0*/ FEATURE_DATA_CALCULATION = 0,
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/*1*/ FEATURE_DPM_CCLK = 1,
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/*2*/ FEATURE_DPM_FCLK = 2,
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/*3*/ FEATURE_DPM_GFXCLK = 3,
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/*4*/ FEATURE_DPM_LCLK = 4,
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/*5*/ FEATURE_DPM_SOCCLK = 5,
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/*6*/ FEATURE_DPM_UCLK = 6,
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/*7*/ FEATURE_DPM_VCN = 7,
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/*8*/ FEATURE_DPM_XGMI = 8,
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/*9*/ FEATURE_DS_FCLK = 9,
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/*10*/ FEATURE_DS_GFXCLK = 10,
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/*11*/ FEATURE_DS_LCLK = 11,
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/*12*/ FEATURE_DS_MP0CLK = 12,
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/*13*/ FEATURE_DS_MP1CLK = 13,
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/*14*/ FEATURE_DS_MPIOCLK = 14,
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/*15*/ FEATURE_DS_SOCCLK = 15,
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/*16*/ FEATURE_DS_VCN = 16,
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/*17*/ FEATURE_APCC_DFLL = 17,
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/*18*/ FEATURE_APCC_PLUS = 18,
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/*19*/ FEATURE_DF_CSTATE = 19,
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/*20*/ FEATURE_CC6 = 20,
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/*21*/ FEATURE_PC6 = 21,
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/*22*/ FEATURE_CPPC = 22,
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/*23*/ FEATURE_PPT = 23,
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/*24*/ FEATURE_TDC = 24,
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/*25*/ FEATURE_THERMAL = 25,
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/*26*/ FEATURE_SOC_PCC = 26,
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/*27*/ FEATURE_CCD_PCC = 27,
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/*28*/ FEATURE_CCD_EDC = 28,
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/*29*/ FEATURE_PROCHOT = 29,
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/*30*/ FEATURE_DVO_CCLK = 30,
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/*31*/ FEATURE_FDD_AID_HBM = 31,
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/*32*/ FEATURE_FDD_AID_SOC = 32,
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/*33*/ FEATURE_FDD_XCD_EDC = 33,
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/*34*/ FEATURE_FDD_XCD_XVMIN = 34,
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/*35*/ FEATURE_FW_CTF = 35,
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/*36*/ FEATURE_GFXOFF = 36,
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/*37*/ FEATURE_SMU_CG = 37,
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/*38*/ FEATURE_PSI7 = 38,
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/*39*/ FEATURE_CSTATE_BOOST = 39,
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/*40*/ FEATURE_XGMI_PER_LINK_PWR_DOWN = 40,
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/*41*/ FEATURE_CXL_QOS = 41,
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/*42*/ FEATURE_SOC_DC_RTC = 42,
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/*43*/ FEATURE_GFX_DC_RTC = 43,
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/*44*/ NUM_FEATURES = 44
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} FEATURE_LIST_e;
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//enum for MPIO PCIe gen speed msgs
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typedef enum {
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PCIE_LINK_SPEED_INDEX_TABLE_GEN1,
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PCIE_LINK_SPEED_INDEX_TABLE_GEN2,
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PCIE_LINK_SPEED_INDEX_TABLE_GEN3,
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PCIE_LINK_SPEED_INDEX_TABLE_GEN4,
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PCIE_LINK_SPEED_INDEX_TABLE_GEN4_ESM,
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PCIE_LINK_SPEED_INDEX_TABLE_GEN5,
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PCIE_LINK_SPEED_INDEX_TABLE_COUNT
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} PCIE_LINK_SPEED_INDEX_TABLE_e;
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typedef enum {
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VOLTAGE_COLD_0,
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VOLTAGE_COLD_1,
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VOLTAGE_COLD_2,
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VOLTAGE_COLD_3,
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VOLTAGE_COLD_4,
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VOLTAGE_COLD_5,
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VOLTAGE_COLD_6,
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VOLTAGE_COLD_7,
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VOLTAGE_MID_0,
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VOLTAGE_MID_1,
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VOLTAGE_MID_2,
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VOLTAGE_MID_3,
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VOLTAGE_MID_4,
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VOLTAGE_MID_5,
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VOLTAGE_MID_6,
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VOLTAGE_MID_7,
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VOLTAGE_HOT_0,
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VOLTAGE_HOT_1,
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VOLTAGE_HOT_2,
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VOLTAGE_HOT_3,
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VOLTAGE_HOT_4,
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VOLTAGE_HOT_5,
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VOLTAGE_HOT_6,
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VOLTAGE_HOT_7,
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VOLTAGE_GUARDBAND_COUNT
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} GFX_GUARDBAND_e;
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#define SMU_METRICS_TABLE_VERSION 0x1
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typedef struct {
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uint32_t AccumulationCounter;
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//TEMPERATURE
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uint32_t MaxSocketTemperature;
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uint32_t MaxVrTemperature;
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uint32_t MaxHbmTemperature;
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uint64_t MaxSocketTemperatureAcc;
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uint64_t MaxVrTemperatureAcc;
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uint64_t MaxHbmTemperatureAcc;
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//POWER
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uint32_t SocketPowerLimit;
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uint32_t MaxSocketPowerLimit;
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uint32_t SocketPower;
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//ENERGY
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uint64_t Timestamp;
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uint64_t SocketEnergyAcc;
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uint64_t CcdEnergyAcc;
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uint64_t XcdEnergyAcc;
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uint64_t AidEnergyAcc;
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uint64_t HbmEnergyAcc;
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//FREQUENCY
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uint32_t CclkFrequencyLimit;
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uint32_t GfxclkFrequencyLimit;
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uint32_t FclkFrequency;
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uint32_t UclkFrequency;
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uint32_t SocclkFrequency[4];
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uint32_t VclkFrequency[4];
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uint32_t DclkFrequency[4];
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uint32_t LclkFrequency[4];
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uint64_t GfxclkFrequencyAcc[8];
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uint64_t CclkFrequencyAcc[96];
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//FREQUENCY RANGE
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uint32_t MaxCclkFrequency;
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uint32_t MinCclkFrequency;
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uint32_t MaxGfxclkFrequency;
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uint32_t MinGfxclkFrequency;
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uint32_t FclkFrequencyTable[4];
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uint32_t UclkFrequencyTable[4];
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uint32_t SocclkFrequencyTable[4];
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uint32_t VclkFrequencyTable[4];
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uint32_t DclkFrequencyTable[4];
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uint32_t LclkFrequencyTable[4];
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uint32_t MaxLclkDpmRange;
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uint32_t MinLclkDpmRange;
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//XGMI
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uint32_t XgmiWidth;
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uint32_t XgmiBitrate;
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uint64_t XgmiReadBandwidthAcc[8];
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uint64_t XgmiWriteBandwidthAcc[8];
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//ACTIVITY
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uint32_t SocketC0Residency;
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uint32_t SocketGfxBusy;
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uint32_t DramBandwidthUtilization;
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uint64_t SocketC0ResidencyAcc;
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uint64_t SocketGfxBusyAcc;
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uint64_t DramBandwidthAcc;
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uint32_t MaxDramBandwidth;
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uint64_t DramBandwidthUtilizationAcc;
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uint64_t PcieBandwidthAcc[4];
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//THROTTLERS
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uint32_t ProchotResidencyAcc;
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uint32_t PptResidencyAcc;
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uint32_t SocketThmResidencyAcc;
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uint32_t VrThmResidencyAcc;
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uint32_t HbmThmResidencyAcc;
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} MetricsTable_t;
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#define SMU_VF_METRICS_TABLE_VERSION 0x1
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typedef struct {
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uint32_t AccumulationCounter;
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uint32_t InstGfxclk_TargFreq;
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uint64_t AccGfxclk_TargFreq;
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uint64_t AccGfxRsmuDpm_Busy;
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} VfMetricsTable_t;
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#endif
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95
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
Normal file
95
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
Normal file
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Copyright 2021 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef SMU_13_0_6_PPSMC_H
|
||||
#define SMU_13_0_6_PPSMC_H
|
||||
|
||||
// SMU Response Codes:
|
||||
#define PPSMC_Result_OK 0x1
|
||||
#define PPSMC_Result_Failed 0xFF
|
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#define PPSMC_Result_UnknownCmd 0xFE
|
||||
#define PPSMC_Result_CmdRejectedPrereq 0xFD
|
||||
#define PPSMC_Result_CmdRejectedBusy 0xFC
|
||||
|
||||
// Message Definitions:
|
||||
#define PPSMC_MSG_TestMessage 0x1
|
||||
#define PPSMC_MSG_GetSmuVersion 0x2
|
||||
#define PPSMC_MSG_GfxDriverReset 0x3
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||||
#define PPSMC_MSG_GetDriverIfVersion 0x4
|
||||
#define PPSMC_MSG_EnableAllSmuFeatures 0x5
|
||||
#define PPSMC_MSG_DisableAllSmuFeatures 0x6
|
||||
#define PPSMC_MSG_RequestI2cTransaction 0x7
|
||||
#define PPSMC_MSG_GetMetricsVersion 0x8
|
||||
#define PPSMC_MSG_GetMetricsTable 0x9
|
||||
#define PPSMC_MSG_GetEccInfoTable 0xA
|
||||
#define PPSMC_MSG_GetEnabledSmuFeaturesLow 0xB
|
||||
#define PPSMC_MSG_GetEnabledSmuFeaturesHigh 0xC
|
||||
#define PPSMC_MSG_SetDriverDramAddrHigh 0xD
|
||||
#define PPSMC_MSG_SetDriverDramAddrLow 0xE
|
||||
#define PPSMC_MSG_SetToolsDramAddrHigh 0xF
|
||||
#define PPSMC_MSG_SetToolsDramAddrLow 0x10
|
||||
#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x11
|
||||
#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x12
|
||||
#define PPSMC_MSG_SetSoftMinByFreq 0x13
|
||||
#define PPSMC_MSG_SetSoftMaxByFreq 0x14
|
||||
#define PPSMC_MSG_GetMinDpmFreq 0x15
|
||||
#define PPSMC_MSG_GetMaxDpmFreq 0x16
|
||||
#define PPSMC_MSG_GetDpmFreqByIndex 0x17
|
||||
#define PPSMC_MSG_SetPptLimit 0x18
|
||||
#define PPSMC_MSG_GetPptLimit 0x19
|
||||
#define PPSMC_MSG_DramLogSetDramAddrHigh 0x1A
|
||||
#define PPSMC_MSG_DramLogSetDramAddrLow 0x1B
|
||||
#define PPSMC_MSG_DramLogSetDramSize 0x1C
|
||||
#define PPSMC_MSG_GetDebugData 0x1D
|
||||
#define PPSMC_MSG_HeavySBR 0x1E
|
||||
#define PPSMC_MSG_SetNumBadHbmPagesRetired 0x1F
|
||||
#define PPSMC_MSG_DFCstateControl 0x20
|
||||
#define PPSMC_MSG_GetGmiPwrDnHyst 0x21
|
||||
#define PPSMC_MSG_SetGmiPwrDnHyst 0x22
|
||||
#define PPSMC_MSG_GmiPwrDnControl 0x23
|
||||
#define PPSMC_MSG_EnterGfxoff 0x24
|
||||
#define PPSMC_MSG_ExitGfxoff 0x25
|
||||
#define PPSMC_MSG_EnableDeterminism 0x26
|
||||
#define PPSMC_MSG_DisableDeterminism 0x27
|
||||
#define PPSMC_MSG_DumpSTBtoDram 0x28
|
||||
#define PPSMC_MSG_STBtoDramLogSetDramAddrHigh 0x29
|
||||
#define PPSMC_MSG_STBtoDramLogSetDramAddrLow 0x2A
|
||||
#define PPSMC_MSG_STBtoDramLogSetDramSize 0x2B
|
||||
#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrHigh 0x2C
|
||||
#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow 0x2D
|
||||
#define PPSMC_MSG_GfxDriverResetRecovery 0x2E
|
||||
#define PPSMC_MSG_TriggerVFFLR 0x2F
|
||||
#define PPSMC_MSG_SetSoftMinGfxClk 0x30
|
||||
#define PPSMC_MSG_SetSoftMaxGfxClk 0x31
|
||||
#define PPSMC_MSG_GetMinGfxDpmFreq 0x32
|
||||
#define PPSMC_MSG_GetMaxGfxDpmFreq 0x33
|
||||
#define PPSMC_Message_Count 0x34
|
||||
|
||||
//PPSMC Reset Types for driver msg argument
|
||||
#define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1
|
||||
#define PPSMC_RESET_TYPE_DRIVER_MODE_2_RESET 0x2
|
||||
#define PPSMC_RESET_TYPE_DRIVER_MODE_3_RESET 0x3
|
||||
|
||||
typedef uint32_t PPSMC_Result;
|
||||
typedef uint32_t PPSMC_MSG;
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user