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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-01-18 16:28:10 -05:00
i2c: designware: Move interrupt handling functions before i2c_dw_xfer()
Code is more logically arranged when i2c_dw_read_clear_intrbits() and i2c_dw_isr() are located before i2c_dw_xfer(). Real reason for this is to prepare for more shared code between interrupt and polling mode code. While at it, remove one extra space and refer to the i2c_dw_init_master() in two comment sections. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Tested-by: Jiawen Wu <jiawenwu@trustnetic.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
This commit is contained in:
Jarkko Nikula
committed by
Andi Shyti
Andi Shyti
parent
04c71da4a9
commit
bd002efaa1
@@ -633,119 +633,6 @@ i2c_dw_read(struct dw_i2c_dev *dev)
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}
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}
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/*
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* Prepare controller for a transaction and call i2c_dw_xfer_msg.
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*/
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static int
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i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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{
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struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
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int ret;
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dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
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pm_runtime_get_sync(dev->dev);
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/*
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* Initiate I2C message transfer when polling mode is enabled,
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* As it is polling based transfer mechanism, which does not support
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* interrupt based functionalities of existing DesignWare driver.
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*/
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switch (dev->flags & MODEL_MASK) {
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case MODEL_AMD_NAVI_GPU:
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ret = amd_i2c_dw_xfer_quirk(adap, msgs, num);
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goto done_nolock;
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case MODEL_WANGXUN_SP:
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ret = txgbe_i2c_dw_xfer_quirk(adap, msgs, num);
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goto done_nolock;
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default:
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break;
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}
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reinit_completion(&dev->cmd_complete);
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dev->msgs = msgs;
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dev->msgs_num = num;
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dev->cmd_err = 0;
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dev->msg_write_idx = 0;
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dev->msg_read_idx = 0;
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dev->msg_err = 0;
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dev->status = 0;
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dev->abort_source = 0;
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dev->rx_outstanding = 0;
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ret = i2c_dw_acquire_lock(dev);
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if (ret)
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goto done_nolock;
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ret = i2c_dw_wait_bus_not_busy(dev);
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if (ret < 0)
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goto done;
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/* Start the transfers */
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i2c_dw_xfer_init(dev);
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/* Wait for tx to complete */
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if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
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dev_err(dev->dev, "controller timed out\n");
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/* i2c_dw_init implicitly disables the adapter */
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i2c_recover_bus(&dev->adapter);
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i2c_dw_init_master(dev);
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ret = -ETIMEDOUT;
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goto done;
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}
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/*
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* We must disable the adapter before returning and signaling the end
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* of the current transfer. Otherwise the hardware might continue
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* generating interrupts which in turn causes a race condition with
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* the following transfer. Needs some more investigation if the
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* additional interrupts are a hardware bug or this driver doesn't
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* handle them correctly yet.
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*/
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__i2c_dw_disable_nowait(dev);
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if (dev->msg_err) {
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ret = dev->msg_err;
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goto done;
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}
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/* No error */
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if (likely(!dev->cmd_err && !dev->status)) {
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ret = num;
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goto done;
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}
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/* We have an error */
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if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
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ret = i2c_dw_handle_tx_abort(dev);
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goto done;
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}
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if (dev->status)
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dev_err(dev->dev,
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"transfer terminated early - interrupt latency too high?\n");
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ret = -EIO;
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done:
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i2c_dw_release_lock(dev);
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done_nolock:
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pm_runtime_mark_last_busy(dev->dev);
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pm_runtime_put_autosuspend(dev->dev);
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return ret;
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}
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static const struct i2c_algorithm i2c_dw_algo = {
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.master_xfer = i2c_dw_xfer,
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.functionality = i2c_dw_func,
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};
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static const struct i2c_adapter_quirks i2c_dw_quirks = {
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.flags = I2C_AQ_NO_ZERO_LEN,
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};
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static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
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{
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unsigned int stat, dummy;
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@@ -872,6 +759,119 @@ static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
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return IRQ_HANDLED;
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}
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/*
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* Prepare controller for a transaction and call i2c_dw_xfer_msg.
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*/
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static int
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i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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{
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struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
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int ret;
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dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
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pm_runtime_get_sync(dev->dev);
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/*
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* Initiate I2C message transfer when polling mode is enabled,
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* As it is polling based transfer mechanism, which does not support
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* interrupt based functionalities of existing DesignWare driver.
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*/
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switch (dev->flags & MODEL_MASK) {
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case MODEL_AMD_NAVI_GPU:
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ret = amd_i2c_dw_xfer_quirk(adap, msgs, num);
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goto done_nolock;
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case MODEL_WANGXUN_SP:
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ret = txgbe_i2c_dw_xfer_quirk(adap, msgs, num);
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goto done_nolock;
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default:
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break;
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}
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reinit_completion(&dev->cmd_complete);
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dev->msgs = msgs;
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dev->msgs_num = num;
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dev->cmd_err = 0;
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dev->msg_write_idx = 0;
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dev->msg_read_idx = 0;
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dev->msg_err = 0;
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dev->status = 0;
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dev->abort_source = 0;
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dev->rx_outstanding = 0;
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ret = i2c_dw_acquire_lock(dev);
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if (ret)
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goto done_nolock;
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ret = i2c_dw_wait_bus_not_busy(dev);
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if (ret < 0)
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goto done;
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/* Start the transfers */
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i2c_dw_xfer_init(dev);
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/* Wait for tx to complete */
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if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
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dev_err(dev->dev, "controller timed out\n");
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/* i2c_dw_init_master() implicitly disables the adapter */
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i2c_recover_bus(&dev->adapter);
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i2c_dw_init_master(dev);
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ret = -ETIMEDOUT;
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goto done;
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}
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/*
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* We must disable the adapter before returning and signaling the end
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* of the current transfer. Otherwise the hardware might continue
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* generating interrupts which in turn causes a race condition with
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* the following transfer. Needs some more investigation if the
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* additional interrupts are a hardware bug or this driver doesn't
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* handle them correctly yet.
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*/
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__i2c_dw_disable_nowait(dev);
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if (dev->msg_err) {
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ret = dev->msg_err;
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goto done;
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}
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/* No error */
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if (likely(!dev->cmd_err && !dev->status)) {
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ret = num;
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goto done;
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}
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/* We have an error */
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if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
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ret = i2c_dw_handle_tx_abort(dev);
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goto done;
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}
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if (dev->status)
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dev_err(dev->dev,
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"transfer terminated early - interrupt latency too high?\n");
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ret = -EIO;
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done:
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i2c_dw_release_lock(dev);
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done_nolock:
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pm_runtime_mark_last_busy(dev->dev);
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pm_runtime_put_autosuspend(dev->dev);
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return ret;
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}
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static const struct i2c_algorithm i2c_dw_algo = {
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.master_xfer = i2c_dw_xfer,
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.functionality = i2c_dw_func,
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};
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static const struct i2c_adapter_quirks i2c_dw_quirks = {
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.flags = I2C_AQ_NO_ZERO_LEN,
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};
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void i2c_dw_configure_master(struct dw_i2c_dev *dev)
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{
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struct i2c_timings *t = &dev->timings;
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