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perf vendor events: Update nehalemex events

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Update event topic moving other topic events to cache and virtual
memory.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andreas Färber <afaerber@suse.de>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Weilin Wang <weilin.wang@intel.com>
Link: https://lore.kernel.org/r/20250328175006.43110-25-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers
2025-03-28 10:49:55 -07:00
committed by Arnaldo Carvalho de Melo
parent c7453cb57b
commit bce986466f
3 changed files with 40 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
tools/perf/pmu-events/arch/x86/nehalemex/cache.json
View File

@@ -239,6 +239,38 @@
"SampleAfterValue": "100000",
"UMask": "0x2"
},
{
"BriefDescription": "L1I instruction fetch stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
"UMask": "0x4"
},
{
"BriefDescription": "L1I instruction fetch hits",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "L1I instruction fetch misses",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "L1I Instruction fetches",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
"UMask": "0x3"
},
{
"BriefDescription": "All L2 data requests",
"Counter": "0,1,2,3",

40
tools/perf/pmu-events/arch/x86/nehalemex/other.json
View File

@@ -15,46 +15,6 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "L1I instruction fetch stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
"UMask": "0x4"
},
{
"BriefDescription": "L1I instruction fetch hits",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "L1I instruction fetch misses",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "L1I Instruction fetches",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
"UMask": "0x3"
},
{
"BriefDescription": "Large ITLB hit",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
"UMask": "0x1"
},
{
"BriefDescription": "All loads dispatched",
"Counter": "0,1,2,3",

8
tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json
View File

@@ -88,6 +88,14 @@
"SampleAfterValue": "200000",
"UMask": "0x20"
},
{
"BriefDescription": "Large ITLB hit",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
"UMask": "0x1"
},
{
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
"Counter": "0,1,2,3",