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drm/amd/pm: update smu_v13_0_6 ppsmc header

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update smu header to support mca dump interface.

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yang Wang
2023-09-04 15:45:02 +08:00
committed by Alex Deucher
parent 5f248462c6
commit bcd8dc49c0
4 changed files with 100 additions and 2 deletions
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88
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h
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@@ -65,6 +65,94 @@ typedef enum {
#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT)
#define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT)
typedef enum {
// MMHUB
CODE_DAGB0,
CODE_EA0 = 5,
CODE_UTCL2_ROUTER = 10,
CODE_VML2,
CODE_VML2_WALKER,
CODE_MMCANE,
// VCN
// VCN VCPU
CODE_VIDD,
CODE_VIDV,
// VCN JPEG
CODE_JPEG0S,
CODE_JPEG0D,
CODE_JPEG1S,
CODE_JPEG1D,
CODE_JPEG2S,
CODE_JPEG2D,
CODE_JPEG3S,
CODE_JPEG3D,
CODE_JPEG4S,
CODE_JPEG4D,
CODE_JPEG5S,
CODE_JPEG5D,
CODE_JPEG6S,
CODE_JPEG6D,
CODE_JPEG7S,
CODE_JPEG7D,
// VCN MMSCH
CODE_MMSCHD,
// SDMA
CODE_SDMA0,
CODE_SDMA1,
CODE_SDMA2,
CODE_SDMA3,
// SOC
CODE_HDP,
CODE_ATHUB,
CODE_IH,
CODE_XHUB_POISON,
CODE_SMN_SLVERR = 40,
CODE_WDT,
CODE_UNKNOWN = 42,
CODE_COUNT,
} ERR_CODE_e;
typedef enum {
// SH POISON FED
SH_FED_CODE,
// GCEA Pin UE_ERR regs
GCEA_CODE,
SQ_CODE,
LDS_CODE,
GDS_CODE,
SP0_CODE,
SP1_CODE,
TCC_CODE,
TCA_CODE,
TCX_CODE,
CPC_CODE,
CPF_CODE,
CPG_CODE,
SPI_CODE,
RLC_CODE,
// GCEA Pin, UE_EDC regs
SQC_CODE,
TA_CODE,
TD_CODE,
TCP_CODE,
TCI_CODE,
// GC Router
GC_ROUTER_CODE,
VML2_CODE,
VML2_WALKER_CODE,
ATCL2_CODE,
GC_CANE_CODE,
// SOC error codes 40-42 are common with ERR_CODE_e
MP5_CODE_SMN_SLVERR = 40,
MP5_CODE_UNKNOWN = 42,
} GC_ERROR_CODE_e;
typedef struct {
uint8_t ReadWriteData; //Return data for read. Data to send for write
uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write

4
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
View File

@@ -88,7 +88,9 @@
#define PPSMC_MSG_McaBankDumpDW 0x37
#define PPSMC_MSG_GetCTFLimit 0x38
#define PPSMC_MSG_ClearMcaOnRead 0x39
#define PPSMC_Message_Count 0x40
#define PPSMC_MSG_QueryValidMcaCeCount 0x3A
#define PPSMC_MSG_McaBankCeDumpDW 0x3B
#define PPSMC_Message_Count 0x41
//PPSMC Reset Types for driver msg argument
#define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1

6
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
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@@ -248,7 +248,11 @@
__SMU_DUMMY_MAP(RequestI2cTransaction), \
__SMU_DUMMY_MAP(GetMetricsTable), \
__SMU_DUMMY_MAP(DALNotPresent), \
__SMU_DUMMY_MAP(ClearMcaOnRead),
__SMU_DUMMY_MAP(ClearMcaOnRead), \
__SMU_DUMMY_MAP(QueryValidMcaCount), \
__SMU_DUMMY_MAP(QueryValidMcaCeCount), \
__SMU_DUMMY_MAP(McaBankDumpDW), \
__SMU_DUMMY_MAP(McaBankCeDumpDW),
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) SMU_MSG_##type

4
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
View File

@@ -136,6 +136,10 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU
MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0),
MSG_MAP(GetCTFLimit, PPSMC_MSG_GetCTFLimit, 0),
MSG_MAP(ClearMcaOnRead, PPSMC_MSG_ClearMcaOnRead, 0),
MSG_MAP(QueryValidMcaCount, PPSMC_MSG_QueryValidMcaCount, 0),
MSG_MAP(QueryValidMcaCeCount, PPSMC_MSG_QueryValidMcaCeCount, 0),
MSG_MAP(McaBankDumpDW, PPSMC_MSG_McaBankDumpDW, 0),
MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, 0),
};
static const struct cmn2asic_mapping smu_v13_0_6_clk_map[SMU_CLK_COUNT] = {