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Merge tag 'meson-clk-5.2' of https://github.com/BayLibre/clk-meson into clk-meson

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Pull Amlogic Meson clk driver updates from Neil Armstrong:

 - Adds VPU and Video Decoder clocks on Meson8b
 - Finally remove the wrong ABP Meson8b clock id
 - Adds Video Decoder, PCIe PLL & CPU Clocks on G12A
 - Re-expose SAR_ADC_SEL and CTS_OSCIN on G12A AO clock controller
 - Un-expose some AXG-Audio input clocks IDs

* tag 'meson-clk-5.2' of https://github.com/BayLibre/clk-meson:
  clk: meson: meson8b: add the video decoder clock trees
  clk: meson: meson8b: add the VPU clock trees
  clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
  clk: meson: meson8b: use a separate clock table for Meson8m2
  clk: meson-g12a: add video decoder clocks
  clk: meson-g12a: add PCIE PLL clocks
  clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
  clk: meson: g12a: add cpu clocks
  dt-bindings: clock: meson8b: export the video decoder clocks
  dt-bindings: clock: meson8b: export the VPU clock
  dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
  dt-bindings: clock: meson8b: drop the "ABP" clock definition
  dt-bindings: clk: g12a-clkc: add VDEC clock IDs
  dt-bindings: clock: axg-audio: unexpose controller inputs
  dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID
  clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id
  clk: meson-g12a: add cpu clock bindings
This commit is contained in:
Stephen Boyd
2019-04-10 15:59:11 -07:00
parent 9e98c678c2 90751f686e
commit bc840f3357
12 changed files with 1479 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/clk/meson/axg-audio.h
View File

@@ -60,6 +60,26 @@
#define AUD_CLKID_MST5 6
#define AUD_CLKID_MST6 7
#define AUD_CLKID_MST7 8
#define AUD_CLKID_SLV_SCLK0 9
#define AUD_CLKID_SLV_SCLK1 10
#define AUD_CLKID_SLV_SCLK2 11
#define AUD_CLKID_SLV_SCLK3 12
#define AUD_CLKID_SLV_SCLK4 13
#define AUD_CLKID_SLV_SCLK5 14
#define AUD_CLKID_SLV_SCLK6 15
#define AUD_CLKID_SLV_SCLK7 16
#define AUD_CLKID_SLV_SCLK8 17
#define AUD_CLKID_SLV_SCLK9 18
#define AUD_CLKID_SLV_LRCLK0 19
#define AUD_CLKID_SLV_LRCLK1 20
#define AUD_CLKID_SLV_LRCLK2 21
#define AUD_CLKID_SLV_LRCLK3 22
#define AUD_CLKID_SLV_LRCLK4 23
#define AUD_CLKID_SLV_LRCLK5 24
#define AUD_CLKID_SLV_LRCLK6 25
#define AUD_CLKID_SLV_LRCLK7 26
#define AUD_CLKID_SLV_LRCLK8 27
#define AUD_CLKID_SLV_LRCLK9 28
#define AUD_CLKID_MST_A_MCLK_SEL 59
#define AUD_CLKID_MST_B_MCLK_SEL 60
#define AUD_CLKID_MST_C_MCLK_SEL 61

26
drivers/clk/meson/clk-pll.c
View File

@@ -303,6 +303,16 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw)
return 1;
}
static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
{
meson_clk_pll_init(hw);
if (meson_clk_pll_wait_lock(hw))
return -EIO;
return 0;
}
static int meson_clk_pll_enable(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
@@ -387,6 +397,22 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
/*
* The Meson G12A PCIE PLL is fined tuned to deliver a very precise
* 100MHz reference clock for the PCIe Analog PHY, and thus requires
* a strict register sequence to enable the PLL.
* To simplify, re-use the _init() op to enable the PLL and keep
* the other ops except set_rate since the rate is fixed.
*/
const struct clk_ops meson_clk_pcie_pll_ops = {
.recalc_rate = meson_clk_pll_recalc_rate,
.round_rate = meson_clk_pll_round_rate,
.is_enabled = meson_clk_pll_is_enabled,
.enable = meson_clk_pcie_pll_enable,
.disable = meson_clk_pll_disable
};
EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops);
const struct clk_ops meson_clk_pll_ops = {
.init = meson_clk_pll_init,
.recalc_rate = meson_clk_pll_recalc_rate,

1
drivers/clk/meson/clk-pll.h
View File

@@ -45,5 +45,6 @@ struct meson_clk_pll_data {
extern const struct clk_ops meson_clk_pll_ro_ops;
extern const struct clk_ops meson_clk_pll_ops;
extern const struct clk_ops meson_clk_pcie_pll_ops;
#endif /* __MESON_CLK_PLL_H */

2
drivers/clk/meson/g12a-aoclk.h
View File

@@ -16,9 +16,7 @@
* to expose, such as the internal muxes and dividers of composite clocks,
* will remain defined here.
*/
#define CLKID_AO_SAR_ADC_SEL 16
#define CLKID_AO_SAR_ADC_DIV 17
#define CLKID_AO_CTS_OSCIN 19
#define CLKID_AO_32K_PRE 20
#define CLKID_AO_32K_DIV 21
#define CLKID_AO_32K_SEL 22

631
drivers/clk/meson/g12a.c
View File

@@ -150,6 +150,318 @@ static struct clk_regmap g12a_sys_pll = {
},
};
static struct clk_regmap g12a_sys_pll_div16_en = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_SYS_CPU_CLK_CNTL1,
.bit_idx = 24,
},
.hw.init = &(struct clk_init_data) {
.name = "sys_pll_div16_en",
.ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "sys_pll" },
.num_parents = 1,
/*
* This clock is used to debug the sys_pll range
* Linux should not change it at runtime
*/
},
};
static struct clk_fixed_factor g12a_sys_pll_div16 = {
.mult = 1,
.div = 16,
.hw.init = &(struct clk_init_data){
.name = "sys_pll_div16",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "sys_pll_div16_en" },
.num_parents = 1,
},
};
/* Datasheet names this field as "premux0" */
static struct clk_regmap g12a_cpu_clk_premux0 = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL0,
.mask = 0x3,
.shift = 0,
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn0_sel",
.ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal",
"fclk_div2",
"fclk_div3" },
.num_parents = 3,
},
};
/* Datasheet names this field as "mux0_divn_tcnt" */
static struct clk_regmap g12a_cpu_clk_mux0_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_SYS_CPU_CLK_CNTL0,
.shift = 4,
.width = 6,
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn0_div",
.ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_dyn0_sel" },
.num_parents = 1,
},
};
/* Datasheet names this field as "postmux0" */
static struct clk_regmap g12a_cpu_clk_postmux0 = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL0,
.mask = 0x1,
.shift = 2,
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn0",
.ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_dyn0_sel",
"cpu_clk_dyn0_div" },
.num_parents = 2,
},
};
/* Datasheet names this field as "premux1" */
static struct clk_regmap g12a_cpu_clk_premux1 = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL0,
.mask = 0x3,
.shift = 16,
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn1_sel",
.ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal",
"fclk_div2",
"fclk_div3" },
.num_parents = 3,
},
};
/* Datasheet names this field as "Mux1_divn_tcnt" */
static struct clk_regmap g12a_cpu_clk_mux1_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_SYS_CPU_CLK_CNTL0,
.shift = 20,
.width = 6,
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn1_div",
.ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_dyn1_sel" },
.num_parents = 1,
},
};
/* Datasheet names this field as "postmux1" */
static struct clk_regmap g12a_cpu_clk_postmux1 = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL0,
.mask = 0x1,
.shift = 18,
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn1",
.ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_dyn1_sel",
"cpu_clk_dyn1_div" },
.num_parents = 2,
},
};
/* Datasheet names this field as "Final_dyn_mux_sel" */
static struct clk_regmap g12a_cpu_clk_dyn = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL0,
.mask = 0x1,
.shift = 10,
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn",
.ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_dyn0",
"cpu_clk_dyn1" },
.num_parents = 2,
},
};
/* Datasheet names this field as "Final_mux_sel" */
static struct clk_regmap g12a_cpu_clk = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL0,
.mask = 0x1,
.shift = 11,
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk",
.ops = &clk_regmap_mux_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_dyn",
"sys_pll" },
.num_parents = 2,
},
};
static struct clk_regmap g12a_cpu_clk_div16_en = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_SYS_CPU_CLK_CNTL1,
.bit_idx = 1,
},
.hw.init = &(struct clk_init_data) {
.name = "cpu_clk_div16_en",
.ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpu_clk" },
.num_parents = 1,
/*
* This clock is used to debug the cpu_clk range
* Linux should not change it at runtime
*/
},
};
static struct clk_fixed_factor g12a_cpu_clk_div16 = {
.mult = 1,
.div = 16,
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_div16",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "cpu_clk_div16_en" },
.num_parents = 1,
},
};
static struct clk_regmap g12a_cpu_clk_apb_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_SYS_CPU_CLK_CNTL1,
.shift = 3,
.width = 3,
.flags = CLK_DIVIDER_POWER_OF_TWO,
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_apb_div",
.ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "cpu_clk" },
.num_parents = 1,
},
};
static struct clk_regmap g12a_cpu_clk_apb = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_SYS_CPU_CLK_CNTL1,
.bit_idx = 1,
},
.hw.init = &(struct clk_init_data) {
.name = "cpu_clk_apb",
.ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_apb_div" },
.num_parents = 1,
/*
* This clock is set by the ROM monitor code,
* Linux should not change it at runtime
*/
},
};
static struct clk_regmap g12a_cpu_clk_atb_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_SYS_CPU_CLK_CNTL1,
.shift = 6,
.width = 3,
.flags = CLK_DIVIDER_POWER_OF_TWO,
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_atb_div",
.ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "cpu_clk" },
.num_parents = 1,
},
};
static struct clk_regmap g12a_cpu_clk_atb = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_SYS_CPU_CLK_CNTL1,
.bit_idx = 17,
},
.hw.init = &(struct clk_init_data) {
.name = "cpu_clk_atb",
.ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_atb_div" },
.num_parents = 1,
/*
* This clock is set by the ROM monitor code,
* Linux should not change it at runtime
*/
},
};
static struct clk_regmap g12a_cpu_clk_axi_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_SYS_CPU_CLK_CNTL1,
.shift = 9,
.width = 3,
.flags = CLK_DIVIDER_POWER_OF_TWO,
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_axi_div",
.ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "cpu_clk" },
.num_parents = 1,
},
};
static struct clk_regmap g12a_cpu_clk_axi = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_SYS_CPU_CLK_CNTL1,
.bit_idx = 18,
},
.hw.init = &(struct clk_init_data) {
.name = "cpu_clk_axi",
.ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_axi_div" },
.num_parents = 1,
/*
* This clock is set by the ROM monitor code,
* Linux should not change it at runtime
*/
},
};
static struct clk_regmap g12a_cpu_clk_trace_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_SYS_CPU_CLK_CNTL1,
.shift = 20,
.width = 3,
.flags = CLK_DIVIDER_POWER_OF_TWO,
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_trace_div",
.ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "cpu_clk" },
.num_parents = 1,
},
};
static struct clk_regmap g12a_cpu_clk_trace = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_SYS_CPU_CLK_CNTL1,
.bit_idx = 23,
},
.hw.init = &(struct clk_init_data) {
.name = "cpu_clk_trace",
.ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "cpu_clk_trace_div" },
.num_parents = 1,
/*
* This clock is set by the ROM monitor code,
* Linux should not change it at runtime
*/
},
};
static const struct pll_mult_range g12a_gp0_pll_mult_range = {
.min = 55,
.max = 255,
@@ -302,6 +614,118 @@ static struct clk_regmap g12a_hifi_pll = {
},
};
/*
* The Meson G12A PCIE PLL is fined tuned to deliver a very precise
* 100MHz reference clock for the PCIe Analog PHY, and thus requires
* a strict register sequence to enable the PLL.
*/
static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 },
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 },
{ .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 },
{ .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 },
{ .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 },
{ .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 },
{ .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 },
{ .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 },
{ .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 },
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 },
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 },
{ .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 },
};
/* Keep a single entry table for recalc/round_rate() ops */
static const struct pll_params_table g12a_pcie_pll_table[] = {
PLL_PARAMS(150, 1),
{0, 0},
};
static struct clk_regmap g12a_pcie_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
.reg_off = HHI_PCIE_PLL_CNTL0,
.shift = 28,
.width = 1,
},
.m = {
.reg_off = HHI_PCIE_PLL_CNTL0,
.shift = 0,
.width = 8,
},
.n = {
.reg_off = HHI_PCIE_PLL_CNTL0,
.shift = 10,
.width = 5,
},
.frac = {
.reg_off = HHI_PCIE_PLL_CNTL1,
.shift = 0,
.width = 12,
},
.l = {
.reg_off = HHI_PCIE_PLL_CNTL0,
.shift = 31,
.width = 1,
},
.rst = {
.reg_off = HHI_PCIE_PLL_CNTL0,
.shift = 29,
.width = 1,
},
.table = g12a_pcie_pll_table,
.init_regs = g12a_pcie_pll_init_regs,
.init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
},
.hw.init = &(struct clk_init_data){
.name = "pcie_pll_dco",
.ops = &meson_clk_pcie_pll_ops,
.parent_names = (const char *[]){ IN_PREFIX "xtal" },
.num_parents = 1,
},
};
static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "pcie_pll_dco_div2",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "pcie_pll_dco" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_pcie_pll_od = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_PCIE_PLL_CNTL0,
.shift = 16,
.width = 5,
.flags = CLK_DIVIDER_ROUND_CLOSEST |
CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ALLOW_ZERO,
},
.hw.init = &(struct clk_init_data){
.name = "pcie_pll_od",
.ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "pcie_pll_dco_div2" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_fixed_factor g12a_pcie_pll = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "pcie_pll_pll",
.ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "pcie_pll_od" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_hdmi_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
@@ -1071,6 +1495,151 @@ static struct clk_regmap g12a_vpu = {
},
};
/* VDEC clocks */
static const char * const g12a_vdec_parent_names[] = {
"fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
"hifi_pll", "gp0_pll",
};
static struct clk_regmap g12a_vdec_1_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VDEC_CLK_CNTL,
.mask = 0x7,
.shift = 9,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_1_sel",
.ops = &clk_regmap_mux_ops,
.parent_names = g12a_vdec_parent_names,
.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_vdec_1_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_VDEC_CLK_CNTL,
.shift = 0,
.width = 7,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_1_div",
.ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_1_sel" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_vdec_1 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VDEC_CLK_CNTL,
.bit_idx = 8,
},
.hw.init = &(struct clk_init_data) {
.name = "vdec_1",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_1_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_vdec_hevcf_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VDEC2_CLK_CNTL,
.mask = 0x7,
.shift = 9,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_hevcf_sel",
.ops = &clk_regmap_mux_ops,
.parent_names = g12a_vdec_parent_names,
.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_vdec_hevcf_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_VDEC2_CLK_CNTL,
.shift = 0,
.width = 7,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_hevcf_div",
.ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_hevcf_sel" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_vdec_hevcf = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VDEC2_CLK_CNTL,
.bit_idx = 8,
},
.hw.init = &(struct clk_init_data) {
.name = "vdec_hevcf",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_hevcf_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_vdec_hevc_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VDEC2_CLK_CNTL,
.mask = 0x7,
.shift = 25,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_hevc_sel",
.ops = &clk_regmap_mux_ops,
.parent_names = g12a_vdec_parent_names,
.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_vdec_hevc_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_VDEC2_CLK_CNTL,
.shift = 16,
.width = 7,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_hevc_div",
.ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_hevc_sel" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_vdec_hevc = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VDEC2_CLK_CNTL,
.bit_idx = 24,
},
.hw.init = &(struct clk_init_data) {
.name = "vdec_hevc",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_hevc_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
/* VAPB Clock */
static const char * const g12a_vapb_parent_names[] = {
@@ -2167,6 +2736,39 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
[CLKID_MALI] = &g12a_mali.hw,
[CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw,
[CLKID_MPLL_5OM] = &g12a_mpll_50m.hw,
[CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
[CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
[CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
[CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
[CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
[CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
[CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
[CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
[CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
[CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
[CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
[CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
[CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
[CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
[CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
[CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
[CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
[CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
[CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
[CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
[CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
[CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
[CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
[CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
[CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
[CLKID_VDEC_1] = &g12a_vdec_1.hw,
[CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
[CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
[CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
[CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
[CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
[CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -2335,6 +2937,35 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
&g12a_mali_1,
&g12a_mali,
&g12a_mpll_50m,
&g12a_sys_pll_div16_en,
&g12a_cpu_clk_premux0,
&g12a_cpu_clk_mux0_div,
&g12a_cpu_clk_postmux0,
&g12a_cpu_clk_premux1,
&g12a_cpu_clk_mux1_div,
&g12a_cpu_clk_postmux1,
&g12a_cpu_clk_dyn,
&g12a_cpu_clk,
&g12a_cpu_clk_div16_en,
&g12a_cpu_clk_apb_div,
&g12a_cpu_clk_apb,
&g12a_cpu_clk_atb_div,
&g12a_cpu_clk_atb,
&g12a_cpu_clk_axi_div,
&g12a_cpu_clk_axi,
&g12a_cpu_clk_trace_div,
&g12a_cpu_clk_trace,
&g12a_pcie_pll_od,
&g12a_pcie_pll_dco,
&g12a_vdec_1_sel,
&g12a_vdec_1_div,
&g12a_vdec_1,
&g12a_vdec_hevc_sel,
&g12a_vdec_hevc_div,
&g12a_vdec_hevc,
&g12a_vdec_hevcf_sel,
&g12a_vdec_hevcf_div,
&g12a_vdec_hevcf,
};
static const struct meson_eeclkc_data g12a_clkc_data = {

31
drivers/clk/meson/g12a.h
View File

@@ -50,6 +50,7 @@
#define HHI_GCLK_MPEG2 0x148
#define HHI_GCLK_OTHER 0x150
#define HHI_GCLK_OTHER2 0x154
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
#define HHI_VID_CLK_DIV 0x164
#define HHI_MPEG_CLK_CNTL 0x174
#define HHI_AUD_CLK_CNTL 0x178
@@ -166,8 +167,36 @@
#define CLKID_MALI_0_DIV 170
#define CLKID_MALI_1_DIV 173
#define CLKID_MPLL_5OM_DIV 176
#define CLKID_SYS_PLL_DIV16_EN 178
#define CLKID_SYS_PLL_DIV16 179
#define CLKID_CPU_CLK_DYN0_SEL 180
#define CLKID_CPU_CLK_DYN0_DIV 181
#define CLKID_CPU_CLK_DYN0 182
#define CLKID_CPU_CLK_DYN1_SEL 183
#define CLKID_CPU_CLK_DYN1_DIV 184
#define CLKID_CPU_CLK_DYN1 185
#define CLKID_CPU_CLK_DYN 186
#define CLKID_CPU_CLK_DIV16_EN 188
#define CLKID_CPU_CLK_DIV16 189
#define CLKID_CPU_CLK_APB_DIV 190
#define CLKID_CPU_CLK_APB 191
#define CLKID_CPU_CLK_ATB_DIV 192
#define CLKID_CPU_CLK_ATB 193
#define CLKID_CPU_CLK_AXI_DIV 194
#define CLKID_CPU_CLK_AXI 195
#define CLKID_CPU_CLK_TRACE_DIV 196
#define CLKID_CPU_CLK_TRACE 197
#define CLKID_PCIE_PLL_DCO 198
#define CLKID_PCIE_PLL_DCO_DIV2 199
#define CLKID_PCIE_PLL_OD 200
#define CLKID_VDEC_1_SEL 202
#define CLKID_VDEC_1_DIV 203
#define CLKID_VDEC_HEVC_SEL 205
#define CLKID_VDEC_HEVC_DIV 206
#define CLKID_VDEC_HEVCF_SEL 208
#define CLKID_VDEC_HEVCF_DIV 209
#define NR_CLKS 178
#define NR_CLKS 211
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/g12a-clkc.h>

734
drivers/clk/meson/meson8b.c
View File

@@ -1703,6 +1703,456 @@ static struct clk_regmap meson8b_mali = {
},
};
static const struct pll_params_table meson8m2_gp_pll_params_table[] = {
PLL_PARAMS(182, 3),
{ /* sentinel */ },
};
static struct clk_regmap meson8m2_gp_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
.reg_off = HHI_GP_PLL_CNTL,
.shift = 30,
.width = 1,
},
.m = {
.reg_off = HHI_GP_PLL_CNTL,
.shift = 0,
.width = 9,
},
.n = {
.reg_off = HHI_GP_PLL_CNTL,
.shift = 9,
.width = 5,
},
.l = {
.reg_off = HHI_GP_PLL_CNTL,
.shift = 31,
.width = 1,
},
.rst = {
.reg_off = HHI_GP_PLL_CNTL,
.shift = 29,
.width = 1,
},
.table = meson8m2_gp_pll_params_table,
},
.hw.init = &(struct clk_init_data){
.name = "gp_pll_dco",
.ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ "xtal" },
.num_parents = 1,
},
};
static struct clk_regmap meson8m2_gp_pll = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_GP_PLL_CNTL,
.shift = 16,
.width = 2,
.flags = CLK_DIVIDER_POWER_OF_TWO,
},
.hw.init = &(struct clk_init_data){
.name = "gp_pll",
.ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "gp_pll_dco" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static const char * const mmeson8b_vpu_0_1_parent_names[] = {
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
};
static const char * const mmeson8m2_vpu_0_1_parent_names[] = {
"fclk_div4", "fclk_div3", "fclk_div5", "gp_pll"
};
static struct clk_regmap meson8b_vpu_0_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VPU_CLK_CNTL,
.mask = 0x3,
.shift = 9,
},
.hw.init = &(struct clk_init_data){
.name = "vpu_0_sel",
.ops = &clk_regmap_mux_ops,
.parent_names = mmeson8b_vpu_0_1_parent_names,
.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8m2_vpu_0_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VPU_CLK_CNTL,
.mask = 0x3,
.shift = 9,
},
.hw.init = &(struct clk_init_data){
.name = "vpu_0_sel",
.ops = &clk_regmap_mux_ops,
.parent_names = mmeson8m2_vpu_0_1_parent_names,
.num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vpu_0_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_VPU_CLK_CNTL,
.shift = 0,
.width = 7,
},
.hw.init = &(struct clk_init_data){
.name = "vpu_0_div",
.ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vpu_0_sel" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vpu_0 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VPU_CLK_CNTL,
.bit_idx = 8,
},
.hw.init = &(struct clk_init_data) {
.name = "vpu_0",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vpu_0_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vpu_1_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VPU_CLK_CNTL,
.mask = 0x3,
.shift = 25,
},
.hw.init = &(struct clk_init_data){
.name = "vpu_1_sel",
.ops = &clk_regmap_mux_ops,
.parent_names = mmeson8b_vpu_0_1_parent_names,
.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8m2_vpu_1_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VPU_CLK_CNTL,
.mask = 0x3,
.shift = 25,
},
.hw.init = &(struct clk_init_data){
.name = "vpu_1_sel",
.ops = &clk_regmap_mux_ops,
.parent_names = mmeson8m2_vpu_0_1_parent_names,
.num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vpu_1_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_VPU_CLK_CNTL,
.shift = 16,
.width = 7,
},
.hw.init = &(struct clk_init_data){
.name = "vpu_1_div",
.ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vpu_1_sel" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vpu_1 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VPU_CLK_CNTL,
.bit_idx = 24,
},
.hw.init = &(struct clk_init_data) {
.name = "vpu_1",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vpu_1_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vpu = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VPU_CLK_CNTL,
.mask = 1,
.shift = 31,
},
.hw.init = &(struct clk_init_data){
.name = "vpu",
.ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "vpu_0", "vpu_1" },
.num_parents = 2,
.flags = CLK_SET_RATE_NO_REPARENT,
},
};
static const char * const meson8b_vdec_parent_names[] = {
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "mpll2", "mpll1"
};
static struct clk_regmap meson8b_vdec_1_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VDEC_CLK_CNTL,
.mask = 0x3,
.shift = 9,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_1_sel",
.ops = &clk_regmap_mux_ops,
.parent_names = meson8b_vdec_parent_names,
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_1_1_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_VDEC_CLK_CNTL,
.shift = 0,
.width = 7,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_1_1_div",
.ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_1_sel" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_1_1 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VDEC_CLK_CNTL,
.bit_idx = 8,
},
.hw.init = &(struct clk_init_data) {
.name = "vdec_1_1",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_1_1_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_1_2_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_VDEC3_CLK_CNTL,
.shift = 0,
.width = 7,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_1_2_div",
.ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_1_sel" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_1_2 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VDEC3_CLK_CNTL,
.bit_idx = 8,
},
.hw.init = &(struct clk_init_data) {
.name = "vdec_1_2",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_1_2_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_1 = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VDEC3_CLK_CNTL,
.mask = 0x1,
.shift = 15,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_1",
.ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "vdec_1_1", "vdec_1_2" },
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_hcodec_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VDEC_CLK_CNTL,
.mask = 0x3,
.shift = 25,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_hcodec_sel",
.ops = &clk_regmap_mux_ops,
.parent_names = meson8b_vdec_parent_names,
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_hcodec_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_VDEC_CLK_CNTL,
.shift = 16,
.width = 7,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_hcodec_div",
.ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_hcodec_sel" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_hcodec = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VDEC_CLK_CNTL,
.bit_idx = 24,
},
.hw.init = &(struct clk_init_data) {
.name = "vdec_hcodec",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_hcodec_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_2_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VDEC2_CLK_CNTL,
.mask = 0x3,
.shift = 9,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_2_sel",
.ops = &clk_regmap_mux_ops,
.parent_names = meson8b_vdec_parent_names,
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_2_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_VDEC2_CLK_CNTL,
.shift = 0,
.width = 7,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_2_div",
.ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_2_sel" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_2 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VDEC2_CLK_CNTL,
.bit_idx = 8,
},
.hw.init = &(struct clk_init_data) {
.name = "vdec_2",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_2_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_hevc_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VDEC2_CLK_CNTL,
.mask = 0x3,
.shift = 25,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_hevc_sel",
.ops = &clk_regmap_mux_ops,
.parent_names = meson8b_vdec_parent_names,
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_hevc_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_VDEC2_CLK_CNTL,
.shift = 16,
.width = 7,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_hevc_div",
.ops = &clk_regmap_divider_ops,
.parent_names = (const char *[]){ "vdec_hevc_sel" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_hevc_en = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VDEC2_CLK_CNTL,
.bit_idx = 24,
},
.hw.init = &(struct clk_init_data) {
.name = "vdec_hevc_en",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "vdec_hevc_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_vdec_hevc = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VDEC2_CLK_CNTL,
.mask = 0x1,
.shift = 31,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_hevc",
.ops = &clk_regmap_mux_ops,
/* TODO: The second parent is currently unknown */
.parent_names = (const char *[]){ "vdec_hevc_en" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
/* Everything Else (EE) domain gates */
static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
@@ -1966,6 +2416,22 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
[CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
[CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
[CLKID_MALI] = &meson8b_mali_0.hw,
[CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
[CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
[CLKID_VPU] = &meson8b_vpu_0.hw,
[CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
[CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
[CLKID_VDEC_1] = &meson8b_vdec_1_1.hw,
[CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
[CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
[CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
[CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
[CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
[CLKID_VDEC_2] = &meson8b_vdec_2.hw,
[CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
[CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
[CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
[CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
[CLK_NR_CLKS] = NULL,
},
.num = CLK_NR_CLKS,
@@ -2152,6 +2618,240 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
[CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
[CLKID_MALI_1] = &meson8b_mali_1.hw,
[CLKID_MALI] = &meson8b_mali.hw,
[CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
[CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
[CLKID_VPU_0] = &meson8b_vpu_0.hw,
[CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw,
[CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
[CLKID_VPU_1] = &meson8b_vpu_1.hw,
[CLKID_VPU] = &meson8b_vpu.hw,
[CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
[CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
[CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
[CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
[CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
[CLKID_VDEC_1] = &meson8b_vdec_1.hw,
[CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
[CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
[CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
[CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
[CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
[CLKID_VDEC_2] = &meson8b_vdec_2.hw,
[CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
[CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
[CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
[CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
[CLK_NR_CLKS] = NULL,
},
.num = CLK_NR_CLKS,
};
static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
.hws = {
[CLKID_XTAL] = &meson8b_xtal.hw,
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
[CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
[CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
[CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
[CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
[CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
[CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
[CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
[CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
[CLKID_CLK81] = &meson8b_clk81.hw,
[CLKID_DDR] = &meson8b_ddr.hw,
[CLKID_DOS] = &meson8b_dos.hw,
[CLKID_ISA] = &meson8b_isa.hw,
[CLKID_PL301] = &meson8b_pl301.hw,
[CLKID_PERIPHS] = &meson8b_periphs.hw,
[CLKID_SPICC] = &meson8b_spicc.hw,
[CLKID_I2C] = &meson8b_i2c.hw,
[CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
[CLKID_SMART_CARD] = &meson8b_smart_card.hw,
[CLKID_RNG0] = &meson8b_rng0.hw,
[CLKID_UART0] = &meson8b_uart0.hw,
[CLKID_SDHC] = &meson8b_sdhc.hw,
[CLKID_STREAM] = &meson8b_stream.hw,
[CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
[CLKID_SDIO] = &meson8b_sdio.hw,
[CLKID_ABUF] = &meson8b_abuf.hw,
[CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
[CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
[CLKID_SPI] = &meson8b_spi.hw,
[CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
[CLKID_ETH] = &meson8b_eth.hw,
[CLKID_DEMUX] = &meson8b_demux.hw,
[CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
[CLKID_IEC958] = &meson8b_iec958.hw,
[CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
[CLKID_AMCLK] = &meson8b_amclk.hw,
[CLKID_AIFIFO2] = &meson8b_aififo2.hw,
[CLKID_MIXER] = &meson8b_mixer.hw,
[CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
[CLKID_ADC] = &meson8b_adc.hw,
[CLKID_BLKMV] = &meson8b_blkmv.hw,
[CLKID_AIU] = &meson8b_aiu.hw,
[CLKID_UART1] = &meson8b_uart1.hw,
[CLKID_G2D] = &meson8b_g2d.hw,
[CLKID_USB0] = &meson8b_usb0.hw,
[CLKID_USB1] = &meson8b_usb1.hw,
[CLKID_RESET] = &meson8b_reset.hw,
[CLKID_NAND] = &meson8b_nand.hw,
[CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
[CLKID_USB] = &meson8b_usb.hw,
[CLKID_VDIN1] = &meson8b_vdin1.hw,
[CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
[CLKID_EFUSE] = &meson8b_efuse.hw,
[CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
[CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
[CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
[CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
[CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
[CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
[CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
[CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
[CLKID_DVIN] = &meson8b_dvin.hw,
[CLKID_UART2] = &meson8b_uart2.hw,
[CLKID_SANA] = &meson8b_sana.hw,
[CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
[CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
[CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
[CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
[CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
[CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
[CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
[CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
[CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
[CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
[CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
[CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
[CLKID_ENC480P] = &meson8b_enc480p.hw,
[CLKID_RNG1] = &meson8b_rng1.hw,
[CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
[CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
[CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
[CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
[CLKID_EDP] = &meson8b_edp.hw,
[CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
[CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
[CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
[CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
[CLKID_MPLL0] = &meson8b_mpll0.hw,
[CLKID_MPLL1] = &meson8b_mpll1.hw,
[CLKID_MPLL2] = &meson8b_mpll2.hw,
[CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
[CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
[CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
[CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
[CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
[CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
[CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
[CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
[CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
[CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
[CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
[CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
[CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
[CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
[CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
[CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
[CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
[CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
[CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
[CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
[CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
[CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
[CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
[CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
[CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
[CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
[CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
[CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
[CLKID_APB] = &meson8b_apb_clk_gate.hw,
[CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
[CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
[CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
[CLKID_AXI] = &meson8b_axi_clk_gate.hw,
[CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
[CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
[CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
[CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
[CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
[CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
[CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
[CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
[CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
[CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
[CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
[CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
[CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
[CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
[CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
[CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
[CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
[CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
[CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
[CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
[CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
[CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
[CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
[CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
[CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
[CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
[CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
[CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
[CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
[CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
[CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
[CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
[CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
[CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
[CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
[CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
[CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
[CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
[CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
[CLKID_MALI_0] = &meson8b_mali_0.hw,
[CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
[CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
[CLKID_MALI_1] = &meson8b_mali_1.hw,
[CLKID_MALI] = &meson8b_mali.hw,
[CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw,
[CLKID_GP_PLL] = &meson8m2_gp_pll.hw,
[CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw,
[CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
[CLKID_VPU_0] = &meson8b_vpu_0.hw,
[CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw,
[CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
[CLKID_VPU_1] = &meson8b_vpu_1.hw,
[CLKID_VPU] = &meson8b_vpu.hw,
[CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
[CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
[CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
[CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
[CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
[CLKID_VDEC_1] = &meson8b_vdec_1.hw,
[CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
[CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
[CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
[CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
[CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
[CLKID_VDEC_2] = &meson8b_vdec_2.hw,
[CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
[CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
[CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
[CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
[CLK_NR_CLKS] = NULL,
},
.num = CLK_NR_CLKS,
@@ -2314,6 +3014,33 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
&meson8b_mali_1_div,
&meson8b_mali_1,
&meson8b_mali,
&meson8m2_gp_pll_dco,
&meson8m2_gp_pll,
&meson8b_vpu_0_sel,
&meson8m2_vpu_0_sel,
&meson8b_vpu_0_div,
&meson8b_vpu_0,
&meson8b_vpu_1_sel,
&meson8m2_vpu_1_sel,
&meson8b_vpu_1_div,
&meson8b_vpu_1,
&meson8b_vpu,
&meson8b_vdec_1_sel,
&meson8b_vdec_1_1_div,
&meson8b_vdec_1_1,
&meson8b_vdec_1_2_div,
&meson8b_vdec_1_2,
&meson8b_vdec_1,
&meson8b_vdec_hcodec_sel,
&meson8b_vdec_hcodec_div,
&meson8b_vdec_hcodec,
&meson8b_vdec_2_sel,
&meson8b_vdec_2_div,
&meson8b_vdec_2,
&meson8b_vdec_hevc_sel,
&meson8b_vdec_hevc_div,
&meson8b_vdec_hevc_en,
&meson8b_vdec_hevc,
};
static const struct meson8b_clk_reset_line {
@@ -2558,9 +3285,14 @@ static void __init meson8b_clkc_init(struct device_node *np)
return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
}
static void __init meson8m2_clkc_init(struct device_node *np)
{
return meson8b_clkc_init_common(np, &meson8m2_hw_onecell_data);
}
CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
meson8_clkc_init);
CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
meson8b_clkc_init);
CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
meson8b_clkc_init);
meson8m2_clkc_init);

27
drivers/clk/meson/meson8b.h
View File

@@ -19,6 +19,7 @@
*
* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
*/
#define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
@@ -34,7 +35,11 @@
#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
#define HHI_VPU_CLK_CNTL 0x1bc /* 0x6f offset in data sheet */
#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */
#define HHI_VDEC_CLK_CNTL 0x1e0 /* 0x78 offset in data sheet */
#define HHI_VDEC2_CLK_CNTL 0x1e4 /* 0x79 offset in data sheet */
#define HHI_VDEC3_CLK_CNTL 0x1e8 /* 0x7a offset in data sheet */
#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
@@ -146,8 +151,28 @@
#define CLKID_MALI_1_SEL 178
#define CLKID_MALI_1_DIV 179
#define CLKID_MALI_1 180
#define CLKID_GP_PLL_DCO 181
#define CLKID_GP_PLL 182
#define CLKID_VPU_0_SEL 183
#define CLKID_VPU_0_DIV 184
#define CLKID_VPU_0 185
#define CLKID_VPU_1_SEL 186
#define CLKID_VPU_1_DIV 187
#define CLKID_VPU_1 189
#define CLKID_VDEC_1_SEL 191
#define CLKID_VDEC_1_1_DIV 192
#define CLKID_VDEC_1_1 193
#define CLKID_VDEC_1_2_DIV 194
#define CLKID_VDEC_1_2 195
#define CLKID_VDEC_HCODEC_SEL 197
#define CLKID_VDEC_HCODEC_DIV 198
#define CLKID_VDEC_2_SEL 200
#define CLKID_VDEC_2_DIV 201
#define CLKID_VDEC_HEVC_SEL 203
#define CLKID_VDEC_HEVC_DIV 204
#define CLKID_VDEC_HEVC_EN 205
#define CLK_NR_CLKS 181
#define CLK_NR_CLKS 207
/*
* include the CLKID and RESETID that have

20
include/dt-bindings/clock/axg-audio-clkc.h
View File

@@ -7,26 +7,6 @@
#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
#define __AXG_AUDIO_CLKC_BINDINGS_H
#define AUD_CLKID_SLV_SCLK0 9
#define AUD_CLKID_SLV_SCLK1 10
#define AUD_CLKID_SLV_SCLK2 11
#define AUD_CLKID_SLV_SCLK3 12
#define AUD_CLKID_SLV_SCLK4 13
#define AUD_CLKID_SLV_SCLK5 14
#define AUD_CLKID_SLV_SCLK6 15
#define AUD_CLKID_SLV_SCLK7 16
#define AUD_CLKID_SLV_SCLK8 17
#define AUD_CLKID_SLV_SCLK9 18
#define AUD_CLKID_SLV_LRCLK0 19
#define AUD_CLKID_SLV_LRCLK1 20
#define AUD_CLKID_SLV_LRCLK2 21
#define AUD_CLKID_SLV_LRCLK3 22
#define AUD_CLKID_SLV_LRCLK4 23
#define AUD_CLKID_SLV_LRCLK5 24
#define AUD_CLKID_SLV_LRCLK6 25
#define AUD_CLKID_SLV_LRCLK7 26
#define AUD_CLKID_SLV_LRCLK8 27
#define AUD_CLKID_SLV_LRCLK9 28
#define AUD_CLKID_DDR_ARB 29
#define AUD_CLKID_PDM 30
#define AUD_CLKID_TDMIN_A 31

2
include/dt-bindings/clock/g12a-aoclkc.h
View File

@@ -26,7 +26,9 @@
#define CLKID_AO_M4_FCLK 13
#define CLKID_AO_M4_HCLK 14
#define CLKID_AO_CLK81 15
#define CLKID_AO_SAR_ADC_SEL 16
#define CLKID_AO_SAR_ADC_CLK 18
#define CLKID_AO_CTS_OSCIN 19
#define CLKID_AO_32K 23
#define CLKID_AO_CEC 27
#define CLKID_AO_CTS_RTC_OSCIN 28

5
include/dt-bindings/clock/g12a-clkc.h
View File

@@ -131,5 +131,10 @@
#define CLKID_MALI_1 174
#define CLKID_MALI 175
#define CLKID_MPLL_5OM 177
#define CLKID_CPU_CLK 187
#define CLKID_PCIE_PLL 201
#define CLKID_VDEC_1 204
#define CLKID_VDEC_HEVC 207
#define CLKID_VDEC_HEVCF 210
#endif /* __G12A_CLKC_H */

6
include/dt-bindings/clock/meson8b-clkc.h
View File

@@ -103,10 +103,14 @@
#define CLKID_MPLL1 94
#define CLKID_MPLL2 95
#define CLKID_NAND_CLK 112
#define CLKID_ABP 124
#define CLKID_APB 124
#define CLKID_PERIPH 126
#define CLKID_AXI 128
#define CLKID_L2_DRAM 130
#define CLKID_VPU 190
#define CLKID_VDEC_1 196
#define CLKID_VDEC_HCODEC 199
#define CLKID_VDEC_2 202
#define CLKID_VDEC_HEVC 206
#endif /* __MESON8B_CLKC_H */