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drm/msm/a6xx: Fix IRQ storm during msm_recovery test

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Once a hang is triggered by the msm_recovery test, the gpu error irq
remains asserted and triggers an interrupt storm. In the worst case,
this IRQ storm lands on the CPU core where the hangcheck timer is
scheduled, blocking it from running. This eventually leads to CPU
watchdog timeouts.

To fix this, mask the gpu error irqs during msm_recovery test and
enable them back during the recovery.

Fixes: 5edf2750d9 ("drm/msm: Add debugfs to disable hw err handling")
Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/730660/
Message-ID: <20260605-assorted-fixes-june-v1-5-2caa04f7287c@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
This commit is contained in:
Jie Zhang
2026-06-05 01:38:21 +05:30
committed by Rob Clark
parent d052d0358f
commit bc024d325e
4 changed files with 15 additions and 2 deletions
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5
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
View File

@@ -1275,6 +1275,11 @@ static irqreturn_t a5xx_irq(struct msm_gpu *gpu)
status & ~A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR);
if (priv->disable_err_irq) {
/* Turn off interrupts to avoid interrupt storm */
gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK,
A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS |
A5XX_RBBM_INT_0_MASK_CP_SW);
status &= A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS |
A5XX_RBBM_INT_0_MASK_CP_SW;
}

5
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
View File

@@ -1911,8 +1911,11 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);
if (priv->disable_err_irq)
if (priv->disable_err_irq) {
/* Turn off interrupts to avoid interrupt storm */
gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS);
status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS;
}
if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
a6xx_fault_detect_irq(gpu);

5
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
View File

@@ -1211,8 +1211,11 @@ irqreturn_t a8xx_irq(struct msm_gpu *gpu)
gpu_write(gpu, REG_A8XX_RBBM_INT_CLEAR_CMD, status);
if (priv->disable_err_irq)
if (priv->disable_err_irq) {
/* Turn off interrupts to avoid interrupt storm */
gpu_write(gpu, REG_A8XX_RBBM_INT_0_MASK, A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS);
status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS;
}
if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
a8xx_fault_detect_irq(gpu);

2
drivers/gpu/drm/msm/msm_gpu.c
View File

@@ -552,6 +552,8 @@ static void recover_worker(struct kthread_work *work)
msm_update_fence(ring->fctx, fence);
}
priv->disable_err_irq = false;
gpu->funcs->recover(gpu);
/* retire completed submits, plus the one that hung: */