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drm/amd/display: Include CSC updates in new fast update path

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[Description]
- Missed color / CSC updates in fast update path
  which caused Custom Color to break.
- Add color / CSC updates to new fast update path
  to fix custom color

Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alvin Lee
2023-06-01 20:39:35 -04:00
committed by Alex Deucher
parent da55037afd
commit bbe4418f22
2 changed files with 102 additions and 0 deletions
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70
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
View File

@@ -562,6 +562,29 @@ void hwss_build_fast_sequence(struct dc *dc,
(*num_steps)++;
}
if (current_mpc_pipe->stream->update_flags.bits.out_csc) {
block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;
block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;
block_sequence[*num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;
(*num_steps)++;
if (current_mpc_pipe->stream->csc_color_matrix.enable_adjustment == true) {
block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;
block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix;
block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC;
(*num_steps)++;
} else {
block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;
block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
block_sequence[*num_steps].params.set_ocsc_default_params.color_space = current_mpc_pipe->stream->output_color_space;
block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT;
(*num_steps)++;
}
}
current_mpc_pipe = current_mpc_pipe->bottom_pipe;
}
current_pipe = current_pipe->next_odm_pipe;
@@ -661,6 +684,15 @@ void hwss_execute_sequence(struct dc *dc,
params->update_visual_confirm_params.pipe_ctx,
params->update_visual_confirm_params.mpcc_id);
break;
case MPC_POWER_ON_MPC_MEM_PWR:
hwss_power_on_mpc_mem_pwr(params);
break;
case MPC_SET_OUTPUT_CSC:
hwss_set_output_csc(params);
break;
case MPC_SET_OCSC_DEFAULT:
hwss_set_ocsc_default(params);
break;
case DMUB_SEND_DMCUB_CMD:
hwss_send_dmcub_cmd(params);
break;
@@ -718,6 +750,44 @@ void hwss_program_bias_and_scale(union block_sequence_params *params)
dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
}
void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params)
{
struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc;
int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id;
bool power_on = params->power_on_mpc_mem_pwr_params.power_on;
if (mpc->funcs->power_on_mpc_mem_pwr)
mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);
}
void hwss_set_output_csc(union block_sequence_params *params)
{
struct mpc *mpc = params->set_output_csc_params.mpc;
int opp_id = params->set_output_csc_params.opp_id;
const uint16_t *matrix = params->set_output_csc_params.regval;
enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode;
if (mpc->funcs->set_output_csc != NULL)
mpc->funcs->set_output_csc(mpc,
opp_id,
matrix,
ocsc_mode);
}
void hwss_set_ocsc_default(union block_sequence_params *params)
{
struct mpc *mpc = params->set_ocsc_default_params.mpc;
int opp_id = params->set_ocsc_default_params.opp_id;
enum dc_color_space colorspace = params->set_ocsc_default_params.color_space;
enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode;
if (mpc->funcs->set_ocsc_default != NULL)
mpc->funcs->set_ocsc_default(mpc,
opp_id,
colorspace,
ocsc_mode);
}
void get_mclk_switch_visual_confirm_color(
struct dc *dc,
struct dc_state *context,

32
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
View File

@@ -114,6 +114,26 @@ struct update_visual_confirm_params {
int mpcc_id;
};
struct power_on_mpc_mem_pwr_params {
struct mpc *mpc;
int mpcc_id;
bool power_on;
};
struct set_output_csc_params {
struct mpc *mpc;
int opp_id;
const uint16_t *regval;
enum mpc_output_csc_mode ocsc_mode;
};
struct set_ocsc_default_params {
struct mpc *mpc;
int opp_id;
enum dc_color_space color_space;
enum mpc_output_csc_mode ocsc_mode;
};
union block_sequence_params {
struct update_plane_addr_params update_plane_addr_params;
struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params;
@@ -128,6 +148,9 @@ union block_sequence_params {
struct program_bias_and_scale_params program_bias_and_scale_params;
struct set_output_transfer_func_params set_output_transfer_func_params;
struct update_visual_confirm_params update_visual_confirm_params;
struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params;
struct set_output_csc_params set_output_csc_params;
struct set_ocsc_default_params set_ocsc_default_params;
};
enum block_sequence_func {
@@ -144,6 +167,9 @@ enum block_sequence_func {
DPP_PROGRAM_BIAS_AND_SCALE,
DPP_SET_OUTPUT_TRANSFER_FUNC,
MPC_UPDATE_VISUAL_CONFIRM,
MPC_POWER_ON_MPC_MEM_PWR,
MPC_SET_OUTPUT_CSC,
MPC_SET_OCSC_DEFAULT,
};
struct block_sequence {
@@ -439,4 +465,10 @@ void hwss_setup_dpp(union block_sequence_params *params);
void hwss_program_bias_and_scale(union block_sequence_params *params);
void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params);
void hwss_set_output_csc(union block_sequence_params *params);
void hwss_set_ocsc_default(union block_sequence_params *params);
#endif /* __DC_HW_SEQUENCER_H__ */