Merge tag 'x86_cleanups_for_v7.3_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 cleanups from Borislav Petkov:

 - The usual pile of smallish cleanups and fixlets all over the place

* tag 'x86_cleanups_for_v7.3_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu: Remove unnecessary __maybe_unused annotations
  x86/msr: Document the I/O-like write semantics in the msr driver
  x86/apic: Ensure ICR register write value is handled as 32 bits
  x86/boot/compressed/head_64.S: Clean up SEV-related comments
  Documentation/arch/x86/amd-memory-encryption.rst: Fix typo
  x86/platform/quark: Fix kernel-doc warnings in imr.c
  x86/ras: Move contents from arch/x86/ras/Kconfig into drivers/ras/Kconfig
  x86/cpu: Move intel_get_platform_id() to cpu/intel.c
  x86/mm: Fix typo in comment
  x86/fpu: Fix kernel-doc formatting above fpu_enable_guest_xfd_features()
  x86/cfi: Use symmetric SYM_START and SYM_END in __CFI_TYPE()
  x86/cfi: Add __init_or_module annotations for fineibt

Documentation/arch/x86/amd-memory-encryption.rst

@@ -53,7 +53,7 @@ CPUID function 0x8000001f reports information related to SME::
 			   system physical addresses, not guest physical
 			   addresses)
 
-If support for SME is present, MSR 0xc00100010 (MSR_AMD64_SYSCFG) can be used to
+If support for SME is present, MSR 0xc0010010 (MSR_AMD64_SYSCFG) can be used to
 determine if SME is enabled and/or to enable memory encryption::
 
 	0xc0010010:

arch/x86/boot/compressed/head_64.S

@@ -172,19 +172,23 @@ SYM_FUNC_START(startup_32)
  /*
   * Build early 4G boot pagetable
   */
-	/*
-	 * If SEV is active then set the encryption mask in the page tables.
-	 * This will ensure that when the kernel is copied and decompressed
-	 * it will be done so encrypted.
-	 */
 	xorl	%edx, %edx
 #ifdef	CONFIG_AMD_MEM_ENCRYPT
 	call	get_sev_encryption_bit
 	xorl	%edx, %edx
 	testl	%eax, %eax
 	jz	1f
-	subl	$32, %eax	/* Encryption bit is always above bit 31 */
-	bts	%eax, %edx	/* Set encryption mask for page tables */
+
+	/* Encryption bit is always above bit 31 */
+	subl	$32, %eax
+
+	/*
+	 * If SEV is active then set the encryption mask in the page tables.
+	 * This will ensure that when the kernel is copied and decompressed it
+	 * will be done so encrypted.
+	 */
+	bts	%eax, %edx
+
 	/*
 	 * Set MSR_AMD64_SEV_ENABLED_BIT in sev_status so that
 	 * startup32_check_sev_cbit() will do a check. sev_enable() will

arch/x86/include/asm/linkage.h

@@ -103,7 +103,7 @@
 	.byte 0xb8 ASM_NL					\
 	.long __kcfi_typeid_##name ASM_NL			\
 	CFI_POST_PADDING					\
-	SYM_FUNC_END(__cfi_##name)
+	SYM_END(__cfi_##name, SYM_T_FUNC)
 
 /* UML needs to be able to override memcpy() and friends for KASAN. */
 #ifdef CONFIG_UML

arch/x86/include/asm/microcode.h

@@ -62,8 +62,6 @@ static inline int intel_microcode_get_datasize(struct microcode_header_intel *hd
 	return hdr->datasize ? : DEFAULT_UCODE_DATASIZE;
 }
 
-extern u32 intel_get_platform_id(void);
-
 static inline u32 intel_get_microcode_revision(void)
 {
 	u32 rev, dummy;

arch/x86/include/asm/processor.h

@@ -238,6 +238,7 @@ extern void early_cpu_init(void);
 extern void identify_secondary_cpu(unsigned int cpu);
 extern void print_cpu_info(struct cpuinfo_x86 *);
 void print_cpu_msr(struct cpuinfo_x86 *);
+extern u32 intel_get_platform_id(void);
 
 /*
  * Friendlier CR3 helpers.

arch/x86/kernel/alternative.c

@@ -1785,8 +1785,8 @@ static int cfi_rewrite_callers(s32 *start, s32 *end)
 #define FINEIBT_WARN(_f, _v) \
 	WARN_ONCE((_f) != (_v), "FineIBT: " #_f " %ld != %d\n", _f, _v)
 
-static void __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline,
-			    s32 *start_cfi, s32 *end_cfi, bool builtin)
+static void __init_or_module __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline,
+					     s32 *start_cfi, s32 *end_cfi, bool builtin)
 {
 	int ret;
 
@@ -2098,8 +2098,8 @@ bool decode_fineibt_insn(struct pt_regs *regs, unsigned long *target, u32 *type)
 
 #else /* !CONFIG_FINEIBT: */
 
-static void __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline,
-			    s32 *start_cfi, s32 *end_cfi, bool builtin)
+static void __init_or_module __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline,
+					     s32 *start_cfi, s32 *end_cfi, bool builtin)
 {
 	if (IS_ENABLED(CONFIG_CFI) && builtin)
 		pr_info("CFI: Using standard kCFI\n");
@@ -2111,8 +2111,8 @@ static void poison_cfi(void *addr) { }
 
 #endif /* !CONFIG_FINEIBT */
 
-void apply_fineibt(s32 *start_retpoline, s32 *end_retpoline,
-		   s32 *start_cfi, s32 *end_cfi)
+void __init_or_module apply_fineibt(s32 *start_retpoline, s32 *end_retpoline,
+				    s32 *start_cfi, s32 *end_cfi)
 {
 	return __apply_fineibt(start_retpoline, end_retpoline,
 			       start_cfi, end_cfi,

arch/x86/kernel/apic/local.h

@@ -44,9 +44,7 @@ static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector,
 #ifdef CONFIG_X86_X2APIC
 static inline void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest)
 {
-	unsigned long cfg = __prepare_ICR(0, vector, dest);
-
-	native_x2apic_icr_write(cfg, apicid);
+	native_x2apic_icr_write(__prepare_ICR(0, vector, dest), apicid);
 }
 #endif
 

arch/x86/kernel/apic/x2apic_phys.c

@@ -85,11 +85,9 @@ static void
 
 static void __x2apic_send_IPI_shorthand(int vector, u32 which)
 {
-	unsigned long cfg = __prepare_ICR(which, vector, 0);
-
 	/* x2apic MSRs are special and need a special fence: */
 	weak_wrmsr_fence();
-	native_x2apic_icr_write(cfg, 0);
+	native_x2apic_icr_write(__prepare_ICR(which, vector, 0), 0);
 }
 
 void x2apic_send_IPI_allbutself(int vector)

arch/x86/kernel/apic/x2apic_savic.c

@@ -243,10 +243,7 @@ static void savic_write(u32 reg, u32 data)
 
 static void send_ipi(u32 dest, unsigned int vector, unsigned int dsh)
 {
-	unsigned int icr_low;
-
-	icr_low = __prepare_ICR(dsh, vector, APIC_DEST_PHYSICAL);
-	savic_icr_write(icr_low, dest);
+	savic_icr_write(__prepare_ICR(dsh, vector, APIC_DEST_PHYSICAL), dest);
 }
 
 static void savic_send_ipi(int cpu, int vector)

arch/x86/kernel/cpu/common.c

@@ -1651,7 +1651,7 @@ static inline bool parse_set_clear_cpuid(char *arg, bool set)
 	int taint = 0;
 
 	while (arg) {
-		bool found __maybe_unused = false;
+		bool found = false;
 		unsigned int bit;
 
 		opt = strsep(&arg, ",");

arch/x86/kernel/cpu/intel.c

@@ -199,6 +199,41 @@ void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c)
 		c->cpuid_level = cpuid_eax(0);
 }
 
+/*
+ * Use CPUID to generate a "vfm" value. Useful before cpuinfo_x86
+ * structures are populated.
+ */
+static u32 intel_cpuid_vfm(void)
+{
+	u32 eax   = cpuid_eax(1);
+	u32 fam   = x86_family(eax);
+	u32 model = x86_model(eax);
+
+	return IFM(fam, model);
+}
+
+u32 intel_get_platform_id(void)
+{
+	unsigned int val[2];
+
+	if (x86_hypervisor_present)
+		return 0;
+
+	/*
+	 * This can be called early. Use CPUID directly instead of
+	 * relying on cpuinfo_x86 which may not be fully initialized.
+	 * The PII does not have MSR_IA32_PLATFORM_ID. Everything
+	 * before _it_ has no microcode (for Linux at least).
+	 */
+	if (intel_cpuid_vfm() <= INTEL_PENTIUM_II_KLAMATH)
+		return 0;
+
+	/* get processor flags from MSR 0x17 */
+	native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
+
+	return (val[1] >> 18) & 7;
+}
+
 static void early_init_intel(struct cpuinfo_x86 *c)
 {
 	u64 misc_enable;

arch/x86/kernel/cpu/microcode/amd.c

@@ -136,8 +136,7 @@ struct cont_desc {
  * Microcode patch container file is prepended to the initrd in cpio
  * format. See Documentation/arch/x86/microcode.rst
  */
-static const char
-ucode_path[] __maybe_unused = "kernel/x86/microcode/AuthenticAMD.bin";
+static const char ucode_path[] = "kernel/x86/microcode/AuthenticAMD.bin";
 
 /*
  * This is CPUID(1).EAX on the BSP. It is used in two ways:

arch/x86/kernel/cpu/microcode/intel.c

@@ -121,42 +121,6 @@ static inline unsigned int exttable_size(struct extended_sigtable *et)
 	return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE;
 }
 
-
-/*
- * Use CPUID to generate a "vfm" value. Useful before cpuinfo_x86
- * structures are populated.
- */
-static u32 intel_cpuid_vfm(void)
-{
-	u32 eax   = cpuid_eax(1);
-	u32 fam   = x86_family(eax);
-	u32 model = x86_model(eax);
-
-	return IFM(fam, model);
-}
-
-u32 intel_get_platform_id(void)
-{
-	unsigned int val[2];
-
-	if (x86_hypervisor_present)
-		return 0;
-
-	/*
-	 * This can be called early. Use CPUID directly instead of
-	 * relying on cpuinfo_x86 which may not be fully initialized.
-	 * The PII does not have MSR_IA32_PLATFORM_ID. Everything
-	 * before _it_ has no microcode (for Linux at least).
-	 */
-	if (intel_cpuid_vfm() <= INTEL_PENTIUM_II_KLAMATH)
-		return 0;
-
-	/* get processor flags from MSR 0x17 */
-	native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
-
-	return (val[1] >> 18) & 7;
-}
-
 void intel_collect_cpu_info(struct cpu_signature *sig)
 {
 	sig->sig = cpuid_eax(1);

arch/x86/kernel/cpu/topology_common.c

@@ -62,7 +62,7 @@ const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c)
 	}
 }
 
-static unsigned int __maybe_unused parse_num_cores_legacy(struct cpuinfo_x86 *c)
+static unsigned int parse_num_cores_legacy(struct cpuinfo_x86 *c)
 {
 	struct {
 		u32	cache_type	:  5,

arch/x86/kernel/fpu/core.c

@@ -294,15 +294,15 @@ void fpu_free_guest_fpstate(struct fpu_guest *gfpu)
 }
 EXPORT_SYMBOL_FOR_KVM(fpu_free_guest_fpstate);
 
-/*
-  * fpu_enable_guest_xfd_features - Check xfeatures against guest perm and enable
-  * @guest_fpu:         Pointer to the guest FPU container
-  * @xfeatures:         Features requested by guest CPUID
-  *
-  * Enable all dynamic xfeatures according to guest perm and requested CPUID.
-  *
-  * Return: 0 on success, error code otherwise
-  */
+/**
+ * fpu_enable_guest_xfd_features - Check xfeatures against guest perm and enable
+ * @guest_fpu:		Pointer to the guest FPU container
+ * @xfeatures:		Features requested by guest CPUID
+ *
+ * Enable all dynamic xfeatures according to guest perm and requested CPUID.
+ *
+ * Return: 0 on success, error code otherwise
+ */
 int fpu_enable_guest_xfd_features(struct fpu_guest *guest_fpu, u64 xfeatures)
 {
 	lockdep_assert_preemption_enabled();

arch/x86/kernel/msr.c

@@ -13,6 +13,9 @@
  * and then read/write in chunks of 8 bytes.  A larger size means multiple
  * reads or writes of the same register.
  *
+ * Writing the same register multiple times can be useful for MSRs with
+ * I/O-like semantics, e.g. a virtual MSR that accepts logging information.
+ *
  * This driver uses /dev/cpu/%d/msr where %d is the minor number, and on
  * an SMP box will direct the access to CPU %d.
  */

arch/x86/mm/ident_map.c

@@ -111,7 +111,7 @@ static int ident_pud_init(struct x86_mapping_info *info, pud_t *pud_page,
 		use_gbpage = info->direct_gbpages;
 
 		/* Don't use gbpage if it maps more than the requested region. */
-		/* at the begining: */
+		/* at the beginning: */
 		use_gbpage &= ((addr & ~PUD_MASK) == 0);
 		/* ... or at the end: */
 		use_gbpage &= ((next & ~PUD_MASK) == 0);

arch/x86/platform/intel-quark/imr.c

@@ -291,8 +291,8 @@ static inline int imr_address_overlap(phys_addr_t addr, struct imr_regs *imr)
  *
  * @base:	physical base address of region aligned to 1KiB.
  * @size:	physical size of region in bytes must be aligned to 1KiB.
- * @read_mask:	read access mask.
- * @write_mask:	write access mask.
+ * @rmask:	read access mask.
+ * @wmask:	write access mask.
  * @return:	zero on success or negative value indicating error.
  */
 int imr_add_range(phys_addr_t base, size_t size,

arch/x86/ras/Kconfig

@@ -1,23 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config RAS_CEC
-	bool "Correctable Errors Collector"
-	depends on X86_MCE && MEMORY_FAILURE && DEBUG_FS
-	help
-	  This is a small cache which collects correctable memory errors per 4K
-	  page PFN and counts their repeated occurrence. Once the counter for a
-	  PFN overflows, we try to soft-offline that page as we take it to mean
-	  that it has reached a relatively high error count and would probably
-	  be best if we don't use it anymore.
-
-	  Bear in mind that this is absolutely useless if your platform doesn't
-	  have ECC DIMMs and doesn't have DRAM ECC checking enabled in the BIOS.
-
-config RAS_CEC_DEBUG
-	bool "CEC debugging machinery"
-	default n
-	depends on RAS_CEC
-	help
-	  Add extra files to (debugfs)/ras/cec to test the correctable error
-	  collector feature. "pfn" is a writable file that allows user to
-	  simulate an error in a particular page frame. "array" is a read-only
-	  file that dumps out the current state of all pages logged so far.

drivers/ras/Kconfig

@@ -31,7 +31,29 @@ menuconfig RAS
 
 if RAS
 
-source "arch/x86/ras/Kconfig"
+config RAS_CEC
+	bool "Correctable Errors Collector"
+	depends on X86_MCE && MEMORY_FAILURE && DEBUG_FS
+	help
+	  This is a small cache which collects correctable memory errors per 4K
+	  page PFN and counts their repeated occurrence. Once the counter for a
+	  PFN overflows, we try to soft-offline that page as we take it to mean
+	  that it has reached a relatively high error count and would probably
+	  be best if we don't use it anymore.
+
+	  Bear in mind that this is absolutely useless if your platform doesn't
+	  have ECC DIMMs and doesn't have DRAM ECC checking enabled in the BIOS.
+
+config RAS_CEC_DEBUG
+	bool "CEC debugging machinery"
+	default n
+	depends on RAS_CEC
+	help
+	  Add extra files to (debugfs)/ras/cec to test the correctable error
+	  collector feature. "pfn" is a writable file that allows user to
+	  simulate an error in a particular page frame. "array" is a read-only
+	  file that dumps out the current state of all pages logged so far.
+
 source "drivers/ras/amd/atl/Kconfig"
 
 config RAS_FMPM