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drm/amd/display: Blank for uclk OC in dm instead of dc

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[Why]
All displays need to be blanked during the uclk OC interface so that we can
guarantee pstate switching support. If the display config doesn't support
pstate switching, only using core_link_disable_stream will not enable it
as the front-end is untouched. We need to go through the full plane removal
sequence to properly program the pipe to allow pstate switching.

[How]
 - guard clk_mgr functions with non-NULL checks

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Joshua Aberback
2020-05-28 11:11:34 -04:00
committed by Alex Deucher
parent ac78fa502a
commit ba8b460445
2 changed files with 14 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@@ -3666,37 +3666,27 @@ void dc_allow_idle_optimizations(struct dc *dc, bool allow)
dc->idle_optimizations_allowed = allow;
}
/*
* blank all streams, and set min and max memory clock to
* lowest and highest DPM level, respectively
*/
/* set min and max memory clock to lowest and highest DPM level, respectively */
void dc_unlock_memory_clock_frequency(struct dc *dc)
{
unsigned int i;
if (dc->clk_mgr->funcs->set_hard_min_memclk)
dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
for (i = 0; i < MAX_PIPES; i++)
if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
if (dc->clk_mgr->funcs->set_hard_max_memclk)
dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
}
/*
* set min memory clock to the min required for current mode,
* max to maxDPM, and unblank streams
*/
/* set min memory clock to the min required for current mode, max to maxDPM */
void dc_lock_memory_clock_frequency(struct dc *dc)
{
unsigned int i;
if (dc->clk_mgr->funcs->get_memclk_states_from_smu)
dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
if (dc->clk_mgr->funcs->set_hard_min_memclk)
dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
for (i = 0; i < MAX_PIPES; i++)
if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
if (dc->clk_mgr->funcs->set_hard_max_memclk)
dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
}
static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz)

10
drivers/gpu/drm/amd/display/dc/dc.h
View File

@@ -1437,16 +1437,10 @@ bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_
void dc_allow_idle_optimizations(struct dc *dc, bool allow);
/*
* blank all streams, and set min and max memory clock to
* lowest and highest DPM level, respectively
*/
/* set min and max memory clock to lowest and highest DPM level, respectively */
void dc_unlock_memory_clock_frequency(struct dc *dc);
/*
* set min memory clock to the min required for current mode,
* max to maxDPM, and unblank streams
*/
/* set min memory clock to the min required for current mode, max to maxDPM */
void dc_lock_memory_clock_frequency(struct dc *dc);
/* set soft max for memclk, to be used for AC/DC switching clock limitations */