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drm/i915/fb: Check that the clear color fits within the BO

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Make sure the user supplied offset[] for the clear color plane
fits within the actual BO. Note that we use tile units to track
the size here. All the other color/aux planes are already
being checked correctly.

Cc: Sagar Ghuge <sagar.ghuge@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Cc: Xi Ruoyao <xry111@xry111.site>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241129065014.8363-4-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
This commit is contained in:
Ville Syrjälä
2024-11-29 08:50:13 +02:00
parent 0bd39e303e
commit b9ec679335
1 changed files with 10 additions and 0 deletions
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10
drivers/gpu/drm/i915/display/intel_fb.c
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@@ -1694,6 +1694,8 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *
* arithmetic related to alignment and offset calculation.
*/
if (is_gen12_ccs_cc_plane(&fb->base, i)) {
unsigned int end;
if (!IS_ALIGNED(fb->base.offsets[i], 64)) {
drm_dbg_kms(&i915->drm,
"fb misaligned clear color plane %d offset (0x%x)\n",
@@ -1701,6 +1703,14 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *
return -EINVAL;
}
if (check_add_overflow(fb->base.offsets[i], 64, &end)) {
drm_dbg_kms(&i915->drm,
"fb bad clear color plane %d offset (0x%x)\n",
i, fb->base.offsets[i]);
return -EINVAL;
}
max_size = max(max_size, DIV_ROUND_UP(end, tile_size));
continue;
}