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powerpc/e500: Always use 64 bits PTE
Today there are two PTE formats for e500: - The 64 bits format, used - On 64 bits kernel - On 32 bits kernel with 64 bits physical addresses - On 32 bits kernel with support of huge pages - The 32 bits format, used in other cases Maintaining two PTE formats means unnecessary maintenance burden because every change needs to be implemented and tested for both formats. Remove the 32 bits PTE format. The memory usage increase due to larger PTEs is minimal (approx. 0,1% of memory). This also means that from now on huge pages are supported also with 32 bits physical addresses. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/04a658209ea78dcc0f3dbde6b2c29cf1939adfe9.1767721208.git.chleroy@kernel.org
This commit is contained in:
Christophe Leroy
committed by
Madhavan Srinivasan
Madhavan Srinivasan
parent
11439c4635
commit
b9e7e3ea60
@@ -120,10 +120,8 @@
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#if defined(CONFIG_44x)
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#include <asm/nohash/32/pte-44x.h>
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#elif defined(CONFIG_PPC_85xx) && defined(CONFIG_PTE_64BIT)
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#include <asm/nohash/pte-e500.h>
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#elif defined(CONFIG_PPC_85xx)
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#include <asm/nohash/32/pte-85xx.h>
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#include <asm/nohash/pte-e500.h>
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#elif defined(CONFIG_PPC_8xx)
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#include <asm/nohash/32/pte-8xx.h>
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#endif
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@@ -1,59 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_NOHASH_32_PTE_85xx_H
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#define _ASM_POWERPC_NOHASH_32_PTE_85xx_H
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#ifdef __KERNEL__
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/* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
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* processors
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*
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MMU Assist Register 3:
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32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
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RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
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- PRESENT *must* be in the bottom two bits because swap PTEs use
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the top 30 bits.
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*/
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/* Definitions for FSL Book-E Cores */
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#define _PAGE_READ 0x00001 /* H: Read permission (SR) */
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#define _PAGE_PRESENT 0x00002 /* S: PTE contains a translation */
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#define _PAGE_WRITE 0x00004 /* S: Write permission (SW) */
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#define _PAGE_DIRTY 0x00008 /* S: Page dirty */
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#define _PAGE_EXEC 0x00010 /* H: SX permission */
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#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
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#define _PAGE_ENDIAN 0x00040 /* H: E bit */
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#define _PAGE_GUARDED 0x00080 /* H: G bit */
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#define _PAGE_COHERENT 0x00100 /* H: M bit */
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#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
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#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
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#define _PAGE_SPECIAL 0x00800 /* S: Special page */
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#define _PMD_PRESENT 0
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#define _PMD_PRESENT_MASK (PAGE_MASK)
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#define _PMD_BAD (~PAGE_MASK)
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#define _PMD_USER 0
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#define _PTE_NONE_MASK 0
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#define PTE_WIMGE_SHIFT (6)
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/*
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* We define 2 sets of base prot bits, one for basic pages (ie,
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* cacheable kernel and user pages) and one for non cacheable
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* pages. We always set _PAGE_COHERENT when SMP is enabled or
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* the processor might need it for DMA coherency.
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*/
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#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
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#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
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#define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT)
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#else
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#define _PAGE_BASE (_PAGE_BASE_NC)
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#endif
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#include <asm/pgtable-masks.h>
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_NOHASH_32_PTE_FSL_85xx_H */
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@@ -49,7 +49,7 @@ static inline unsigned long pud_val(pud_t x)
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#endif /* CONFIG_PPC64 */
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/* PGD level */
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#if defined(CONFIG_PPC_85xx) && defined(CONFIG_PTE_64BIT)
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#if defined(CONFIG_PPC_85xx)
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typedef struct { unsigned long long pgd; } pgd_t;
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static inline unsigned long long pgd_val(pgd_t x)
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@@ -305,7 +305,6 @@ set_ivor:
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* r12 is pointer to the pte
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* r10 is the pshift from the PGD, if we're a hugepage
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*/
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#ifdef CONFIG_PTE_64BIT
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#ifdef CONFIG_HUGETLB_PAGE
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#define FIND_PTE \
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rlwinm r12, r13, 14, 18, 28; /* Compute pgdir/pmd offset */ \
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@@ -329,15 +328,6 @@ set_ivor:
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rlwimi r12, r13, 23, 20, 28; /* Compute pte address */ \
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lwz r11, 4(r12); /* Get pte entry */
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#endif /* HUGEPAGE */
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#else /* !PTE_64BIT */
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#define FIND_PTE \
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rlwimi r11, r13, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
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lwz r11, 0(r11); /* Get L1 entry */ \
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rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
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beq 2f; /* Bail if no table */ \
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rlwimi r12, r13, 22, 20, 29; /* Compute PTE address */ \
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lwz r11, 0(r12); /* Get Linux PTE */
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#endif
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/*
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* Interrupt vector entry code
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@@ -473,21 +463,15 @@ END_BTB_FLUSH_SECTION
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4:
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FIND_PTE
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#ifdef CONFIG_PTE_64BIT
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li r13,_PAGE_PRESENT|_PAGE_BAP_SR
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oris r13,r13,_PAGE_ACCESSED@h
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#else
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li r13,_PAGE_PRESENT|_PAGE_READ|_PAGE_ACCESSED
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#endif
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andc. r13,r13,r11 /* Check permission */
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#ifdef CONFIG_PTE_64BIT
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#ifdef CONFIG_SMP
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subf r13,r11,r12 /* create false data dep */
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lwzx r13,r11,r13 /* Get upper pte bits */
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#else
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lwz r13,0(r12) /* Get upper pte bits */
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#endif
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#endif
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bne 2f /* Bail if permission/valid mismatch */
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@@ -552,12 +536,8 @@ END_BTB_FLUSH_SECTION
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FIND_PTE
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/* Make up the required permissions for kernel code */
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#ifdef CONFIG_PTE_64BIT
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li r13,_PAGE_PRESENT | _PAGE_BAP_SX
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oris r13,r13,_PAGE_ACCESSED@h
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#else
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li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
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#endif
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b 4f
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/* Get the PGD for the current thread */
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@@ -573,23 +553,17 @@ END_BTB_FLUSH_SECTION
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FIND_PTE
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/* Make up the required permissions for user code */
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#ifdef CONFIG_PTE_64BIT
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li r13,_PAGE_PRESENT | _PAGE_BAP_UX
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oris r13,r13,_PAGE_ACCESSED@h
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#else
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li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
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#endif
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4:
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andc. r13,r13,r11 /* Check permission */
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#ifdef CONFIG_PTE_64BIT
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#ifdef CONFIG_SMP
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subf r13,r11,r12 /* create false data dep */
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lwzx r13,r11,r13 /* Get upper pte bits */
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#else
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lwz r13,0(r12) /* Get upper pte bits */
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#endif
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#endif
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bne 2f /* Bail if permission mismatch */
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@@ -683,7 +657,7 @@ interrupt_end:
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* r10 - tsize encoding (if HUGETLB_PAGE) or available to use
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* r11 - TLB (info from Linux PTE)
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* r12 - available to use
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* r13 - upper bits of PTE (if PTE_64BIT) or available to use
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* r13 - upper bits of PTE
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* CR5 - results of addr >= PAGE_OFFSET
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* MAS0, MAS1 - loaded with proper value when we get here
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* MAS2, MAS3 - will need additional info from Linux PTE
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@@ -751,7 +725,6 @@ finish_tlb_load:
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* here we (properly should) assume have the appropriate value.
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*/
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finish_tlb_load_cont:
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#ifdef CONFIG_PTE_64BIT
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rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
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andi. r10, r11, _PAGE_DIRTY
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bne 1f
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@@ -764,26 +737,9 @@ BEGIN_MMU_FTR_SECTION
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srwi r10, r13, 12 /* grab RPN[12:31] */
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mtspr SPRN_MAS7, r10
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
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#else
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li r10, (_PAGE_EXEC | _PAGE_READ)
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mr r13, r11
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rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
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and r12, r11, r10
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mcrf cr0, cr5 /* Test for user page */
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slwi r10, r12, 1
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or r10, r10, r12
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rlwinm r10, r10, 0, ~_PAGE_EXEC /* Clear SX on user pages */
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isellt r12, r10, r12
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rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
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mtspr SPRN_MAS3, r13
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#endif
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mfspr r12, SPRN_MAS2
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#ifdef CONFIG_PTE_64BIT
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rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
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#else
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rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
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#endif
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#ifdef CONFIG_HUGETLB_PAGE
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beq 6, 3f /* don't mask if page isn't huge */
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li r13, 1
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@@ -276,7 +276,7 @@ config PPC_BOOK3S
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config PPC_E500
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select FSL_EMB_PERFMON
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bool
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select ARCH_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64
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select ARCH_SUPPORTS_HUGETLBFS
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select PPC_SMP_MUXED_IPI
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select PPC_DOORBELL
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select PPC_KUEP
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@@ -337,7 +337,7 @@ config BOOKE
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config PTE_64BIT
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bool
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depends on 44x || PPC_E500 || PPC_86xx
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default y if PHYS_64BIT
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default y if PPC_E500 || PHYS_64BIT
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config PHYS_64BIT
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bool 'Large physical address support' if PPC_E500 || PPC_86xx
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