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remoteproc: k3-r5: Re-order internal memory initialization functions
The internal memory struct pointer, 'mem', will be refactored from k3_r5_core struct into k3_r5_rproc struct in a future commit. Therefore, move the internal memory initialization function, k3_r5_core_of_get_internal_memories() above k3_r5_cluster_rproc_init() so that the former can be invoked by the later. While at it, also re-order the k3_r5_core_of_get_sram_memories() to keep all the internal memory initialization functions at one place. Signed-off-by: Beleswar Padhi <b-padhi@ti.com> Tested-by: Judith Mendez <jm@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250513054510.3439842-6-b-padhi@ti.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
This commit is contained in:
Beleswar Padhi
committed by
Mathieu Poirier
Mathieu Poirier
parent
2353252459
commit
b9229c0732
@@ -1227,6 +1227,135 @@ static int k3_r5_rproc_configure_mode(struct k3_r5_rproc *kproc)
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return ret;
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}
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static int k3_r5_core_of_get_internal_memories(struct platform_device *pdev,
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struct k3_r5_core *core)
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{
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static const char * const mem_names[] = {"atcm", "btcm"};
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struct device *dev = &pdev->dev;
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struct resource *res;
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int num_mems;
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int i;
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num_mems = ARRAY_SIZE(mem_names);
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core->mem = devm_kcalloc(dev, num_mems, sizeof(*core->mem), GFP_KERNEL);
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if (!core->mem)
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return -ENOMEM;
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for (i = 0; i < num_mems; i++) {
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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mem_names[i]);
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if (!res) {
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dev_err(dev, "found no memory resource for %s\n",
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mem_names[i]);
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return -EINVAL;
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}
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if (!devm_request_mem_region(dev, res->start,
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resource_size(res),
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dev_name(dev))) {
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dev_err(dev, "could not request %s region for resource\n",
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mem_names[i]);
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return -EBUSY;
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}
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/*
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* TCMs are designed in general to support RAM-like backing
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* memories. So, map these as Normal Non-Cached memories. This
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* also avoids/fixes any potential alignment faults due to
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* unaligned data accesses when using memcpy() or memset()
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* functions (normally seen with device type memory).
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*/
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core->mem[i].cpu_addr = devm_ioremap_wc(dev, res->start,
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resource_size(res));
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if (!core->mem[i].cpu_addr) {
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dev_err(dev, "failed to map %s memory\n", mem_names[i]);
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return -ENOMEM;
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}
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core->mem[i].bus_addr = res->start;
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/*
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* TODO:
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* The R5F cores can place ATCM & BTCM anywhere in its address
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* based on the corresponding Region Registers in the System
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* Control coprocessor. For now, place ATCM and BTCM at
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* addresses 0 and 0x41010000 (same as the bus address on AM65x
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* SoCs) based on loczrama setting
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*/
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if (!strcmp(mem_names[i], "atcm")) {
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core->mem[i].dev_addr = core->loczrama ?
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0 : K3_R5_TCM_DEV_ADDR;
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} else {
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core->mem[i].dev_addr = core->loczrama ?
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K3_R5_TCM_DEV_ADDR : 0;
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}
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core->mem[i].size = resource_size(res);
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dev_dbg(dev, "memory %5s: bus addr %pa size 0x%zx va %pK da 0x%x\n",
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mem_names[i], &core->mem[i].bus_addr,
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core->mem[i].size, core->mem[i].cpu_addr,
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core->mem[i].dev_addr);
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}
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core->num_mems = num_mems;
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return 0;
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}
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static int k3_r5_core_of_get_sram_memories(struct platform_device *pdev,
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struct k3_r5_core *core)
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{
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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struct device_node *sram_np;
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struct resource res;
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int num_sram;
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int i, ret;
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num_sram = of_property_count_elems_of_size(np, "sram", sizeof(phandle));
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if (num_sram <= 0) {
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dev_dbg(dev, "device does not use reserved on-chip memories, num_sram = %d\n",
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num_sram);
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return 0;
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}
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core->sram = devm_kcalloc(dev, num_sram, sizeof(*core->sram), GFP_KERNEL);
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if (!core->sram)
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return -ENOMEM;
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for (i = 0; i < num_sram; i++) {
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sram_np = of_parse_phandle(np, "sram", i);
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if (!sram_np)
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return -EINVAL;
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if (!of_device_is_available(sram_np)) {
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of_node_put(sram_np);
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return -EINVAL;
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}
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ret = of_address_to_resource(sram_np, 0, &res);
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of_node_put(sram_np);
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if (ret)
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return -EINVAL;
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core->sram[i].bus_addr = res.start;
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core->sram[i].dev_addr = res.start;
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core->sram[i].size = resource_size(&res);
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core->sram[i].cpu_addr = devm_ioremap_wc(dev, res.start,
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resource_size(&res));
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if (!core->sram[i].cpu_addr) {
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dev_err(dev, "failed to parse and map sram%d memory at %pad\n",
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i, &res.start);
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return -ENOMEM;
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}
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dev_dbg(dev, "memory sram%d: bus addr %pa size 0x%zx va %pK da 0x%x\n",
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i, &core->sram[i].bus_addr,
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core->sram[i].size, core->sram[i].cpu_addr,
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core->sram[i].dev_addr);
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}
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core->num_sram = num_sram;
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return 0;
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}
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static int k3_r5_cluster_rproc_init(struct platform_device *pdev)
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{
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struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
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@@ -1366,135 +1495,6 @@ static void k3_r5_cluster_rproc_exit(void *data)
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}
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}
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static int k3_r5_core_of_get_internal_memories(struct platform_device *pdev,
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struct k3_r5_core *core)
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{
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static const char * const mem_names[] = {"atcm", "btcm"};
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struct device *dev = &pdev->dev;
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struct resource *res;
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int num_mems;
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int i;
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num_mems = ARRAY_SIZE(mem_names);
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core->mem = devm_kcalloc(dev, num_mems, sizeof(*core->mem), GFP_KERNEL);
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if (!core->mem)
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return -ENOMEM;
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for (i = 0; i < num_mems; i++) {
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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mem_names[i]);
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if (!res) {
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dev_err(dev, "found no memory resource for %s\n",
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mem_names[i]);
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return -EINVAL;
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}
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if (!devm_request_mem_region(dev, res->start,
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resource_size(res),
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dev_name(dev))) {
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dev_err(dev, "could not request %s region for resource\n",
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mem_names[i]);
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return -EBUSY;
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}
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/*
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* TCMs are designed in general to support RAM-like backing
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* memories. So, map these as Normal Non-Cached memories. This
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* also avoids/fixes any potential alignment faults due to
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* unaligned data accesses when using memcpy() or memset()
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* functions (normally seen with device type memory).
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*/
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core->mem[i].cpu_addr = devm_ioremap_wc(dev, res->start,
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resource_size(res));
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if (!core->mem[i].cpu_addr) {
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dev_err(dev, "failed to map %s memory\n", mem_names[i]);
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return -ENOMEM;
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}
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core->mem[i].bus_addr = res->start;
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/*
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* TODO:
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* The R5F cores can place ATCM & BTCM anywhere in its address
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* based on the corresponding Region Registers in the System
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* Control coprocessor. For now, place ATCM and BTCM at
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* addresses 0 and 0x41010000 (same as the bus address on AM65x
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* SoCs) based on loczrama setting
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*/
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if (!strcmp(mem_names[i], "atcm")) {
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core->mem[i].dev_addr = core->loczrama ?
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0 : K3_R5_TCM_DEV_ADDR;
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} else {
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core->mem[i].dev_addr = core->loczrama ?
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K3_R5_TCM_DEV_ADDR : 0;
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}
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core->mem[i].size = resource_size(res);
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dev_dbg(dev, "memory %5s: bus addr %pa size 0x%zx va %pK da 0x%x\n",
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mem_names[i], &core->mem[i].bus_addr,
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core->mem[i].size, core->mem[i].cpu_addr,
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core->mem[i].dev_addr);
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}
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core->num_mems = num_mems;
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return 0;
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}
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static int k3_r5_core_of_get_sram_memories(struct platform_device *pdev,
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struct k3_r5_core *core)
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{
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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struct device_node *sram_np;
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struct resource res;
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int num_sram;
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int i, ret;
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num_sram = of_property_count_elems_of_size(np, "sram", sizeof(phandle));
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if (num_sram <= 0) {
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dev_dbg(dev, "device does not use reserved on-chip memories, num_sram = %d\n",
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num_sram);
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return 0;
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}
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core->sram = devm_kcalloc(dev, num_sram, sizeof(*core->sram), GFP_KERNEL);
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if (!core->sram)
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return -ENOMEM;
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for (i = 0; i < num_sram; i++) {
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sram_np = of_parse_phandle(np, "sram", i);
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if (!sram_np)
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return -EINVAL;
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if (!of_device_is_available(sram_np)) {
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of_node_put(sram_np);
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return -EINVAL;
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}
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ret = of_address_to_resource(sram_np, 0, &res);
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of_node_put(sram_np);
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if (ret)
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return -EINVAL;
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core->sram[i].bus_addr = res.start;
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core->sram[i].dev_addr = res.start;
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core->sram[i].size = resource_size(&res);
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core->sram[i].cpu_addr = devm_ioremap_wc(dev, res.start,
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resource_size(&res));
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if (!core->sram[i].cpu_addr) {
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dev_err(dev, "failed to parse and map sram%d memory at %pad\n",
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i, &res.start);
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return -ENOMEM;
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}
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dev_dbg(dev, "memory sram%d: bus addr %pa size 0x%zx va %pK da 0x%x\n",
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i, &core->sram[i].bus_addr,
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core->sram[i].size, core->sram[i].cpu_addr,
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core->sram[i].dev_addr);
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}
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core->num_sram = num_sram;
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return 0;
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}
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static void k3_r5_release_tsp(void *data)
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{
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struct ti_sci_proc *tsp = data;
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