x86/mce, EDAC/mce_amd: Add new SMCA bank types

Recognize new SMCA bank types and include their short names for sysfs
and long names for decoding.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://patch.msgid.link/20260307163316.345923-4-yazen.ghannam@amd.com

arch/x86/include/asm/mce.h

@@ -352,7 +352,10 @@ extern void apei_mce_report_mem_error(int corrected,
 enum smca_bank_types {
 	SMCA_CS,	/* Coherent Station */
 	SMCA_CS_V2,
+	SMCA_DACC_BE,	/* Data Acceleration Back-end */
+	SMCA_DACC_FE,	/* Data Acceleration Front-end */
 	SMCA_DE,	/* Decoder Unit */
+	SMCA_EDDR5CMN,	/* eDDR5 CMN */
 	SMCA_EX,	/* Execution Unit */
 	SMCA_FP,	/* Floating Point */
 	SMCA_GMI_PCS,	/* GMI PCS Unit */
@@ -364,12 +367,19 @@ enum smca_bank_types {
 	SMCA_LS_V2,
 	SMCA_MA_LLC,	/* Memory Attached Last Level Cache */
 	SMCA_MP5,	/* Microprocessor 5 Unit */
+	SMCA_MPART,	/* AMD Root of Trust Microprocessor */
+	SMCA_MPASP,	/* AMD Secure Processor */
+	SMCA_MPASP_V2,
+	SMCA_MPDACC,	/* MP for Data Acceleration */
 	SMCA_MPDMA,	/* MPDMA Unit */
+	SMCA_MPM,	/* Microprocessor Manageability Core */
+	SMCA_MPRAS,	/* MP for RAS */
 	SMCA_NBIF,	/* NBIF Unit */
 	SMCA_NBIO,	/* Northbridge IO Unit */
 	SMCA_PB,	/* Parameter Block */
 	SMCA_PCIE,	/* PCI Express Unit */
 	SMCA_PCIE_V2,
+	SMCA_PCIE_PL,	/* PCIe Link */
 	SMCA_PIE,	/* Power, Interrupts, etc. */
 	SMCA_PSP,	/* Platform Security Processor */
 	SMCA_PSP_V2,
@@ -378,6 +388,7 @@ enum smca_bank_types {
 	SMCA_SHUB,	/* System HUB Unit */
 	SMCA_SMU,	/* System Management Unit */
 	SMCA_SMU_V2,
+	SMCA_SSBDCI,	/* Die to Die Interconnect */
 	SMCA_UMC,	/* Unified Memory Controller */
 	SMCA_UMC_V2,
 	SMCA_USB,	/* USB Unit */

arch/x86/kernel/cpu/mce/amd.c

@@ -96,7 +96,10 @@ static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts);
 
 static const char * const smca_names[] = {
 	[SMCA_CS ... SMCA_CS_V2]	= "coherent_station",
+	[SMCA_DACC_BE]			= "dacc_be",
+	[SMCA_DACC_FE]			= "dacc_fe",
 	[SMCA_DE]			= "decode_unit",
+	[SMCA_EDDR5CMN]			= "eddr5_cmn",
 	[SMCA_EX]			= "execution_unit",
 	[SMCA_FP]			= "floating_point",
 	[SMCA_GMI_PCS]			= "gmi_pcs",
@@ -107,17 +110,24 @@ static const char * const smca_names[] = {
 	[SMCA_LS ... SMCA_LS_V2]	= "load_store",
 	[SMCA_MA_LLC]			= "ma_llc",
 	[SMCA_MP5]			= "mp5",
+	[SMCA_MPART]			= "mpart",
+	[SMCA_MPASP ... SMCA_MPASP_V2]	= "mpasp",
+	[SMCA_MPDACC]			= "mpdacc",
 	[SMCA_MPDMA]			= "mpdma",
+	[SMCA_MPM]			= "mpm",
+	[SMCA_MPRAS]			= "mpras",
 	[SMCA_NBIF]			= "nbif",
 	[SMCA_NBIO]			= "nbio",
 	[SMCA_PB]			= "param_block",
 	[SMCA_PCIE ... SMCA_PCIE_V2]	= "pcie",
+	[SMCA_PCIE_PL]			= "pcie_pl",
 	[SMCA_PIE]			= "pie",
 	[SMCA_PSP ... SMCA_PSP_V2]	= "psp",
 	[SMCA_RESERVED]			= "reserved",
 	[SMCA_SATA]			= "sata",
 	[SMCA_SHUB]			= "shub",
 	[SMCA_SMU ... SMCA_SMU_V2]	= "smu",
+	[SMCA_SSBDCI]			= "ssbdci",
 
 	/* UMC v2 is separate because both of them can exist in a single system. */
 	[SMCA_UMC]			= "umc",
@@ -162,7 +172,10 @@ EXPORT_SYMBOL_GPL(smca_get_bank_type);
 static const struct smca_hwid smca_hwid_mcatypes[] = {
 	{ SMCA_CS,	 HWID_MCATYPE(0x2E, 0x0)	},
 	{ SMCA_CS_V2,	 HWID_MCATYPE(0x2E, 0x2)	},
+	{ SMCA_DACC_BE,	 HWID_MCATYPE(0x164, 0x0)	},
+	{ SMCA_DACC_FE,	 HWID_MCATYPE(0x157, 0x0)	},
 	{ SMCA_DE,	 HWID_MCATYPE(0xB0, 0x3)	},
+	{ SMCA_EDDR5CMN, HWID_MCATYPE(0x1E0, 0x0)	},
 	{ SMCA_EX,	 HWID_MCATYPE(0xB0, 0x5)	},
 	{ SMCA_FP,	 HWID_MCATYPE(0xB0, 0x6)	},
 	{ SMCA_GMI_PCS,  HWID_MCATYPE(0x241, 0x0)	},
@@ -174,12 +187,19 @@ static const struct smca_hwid smca_hwid_mcatypes[] = {
 	{ SMCA_LS_V2,	 HWID_MCATYPE(0xB0, 0x10)	},
 	{ SMCA_MA_LLC,	 HWID_MCATYPE(0x2E, 0x4)	},
 	{ SMCA_MP5,	 HWID_MCATYPE(0x01, 0x2)	},
+	{ SMCA_MPART,	 HWID_MCATYPE(0xFF, 0x2)	},
+	{ SMCA_MPASP,	 HWID_MCATYPE(0xFD, 0x0)	},
+	{ SMCA_MPASP_V2, HWID_MCATYPE(0xFD, 0x1)	},
+	{ SMCA_MPDACC,	 HWID_MCATYPE(0xBE, 0x0)	},
 	{ SMCA_MPDMA,	 HWID_MCATYPE(0x01, 0x3)	},
+	{ SMCA_MPM,	 HWID_MCATYPE(0xF9, 0x0)	},
+	{ SMCA_MPRAS,	 HWID_MCATYPE(0x12, 0x0)	},
 	{ SMCA_NBIF,	 HWID_MCATYPE(0x6C, 0x0)	},
 	{ SMCA_NBIO,	 HWID_MCATYPE(0x18, 0x0)	},
 	{ SMCA_PB,	 HWID_MCATYPE(0x05, 0x0)	},
 	{ SMCA_PCIE,	 HWID_MCATYPE(0x46, 0x0)	},
 	{ SMCA_PCIE_V2,	 HWID_MCATYPE(0x46, 0x1)	},
+	{ SMCA_PCIE_PL,	 HWID_MCATYPE(0x1E1, 0x0)	},
 	{ SMCA_PIE,	 HWID_MCATYPE(0x2E, 0x1)	},
 	{ SMCA_PSP,	 HWID_MCATYPE(0xFF, 0x0)	},
 	{ SMCA_PSP_V2,	 HWID_MCATYPE(0xFF, 0x1)	},
@@ -188,6 +208,7 @@ static const struct smca_hwid smca_hwid_mcatypes[] = {
 	{ SMCA_SHUB,	 HWID_MCATYPE(0x80, 0x0)	},
 	{ SMCA_SMU,	 HWID_MCATYPE(0x01, 0x0)	},
 	{ SMCA_SMU_V2,	 HWID_MCATYPE(0x01, 0x1)	},
+	{ SMCA_SSBDCI,	 HWID_MCATYPE(0x5C, 0x0)	},
 	{ SMCA_UMC,	 HWID_MCATYPE(0x96, 0x0)	},
 	{ SMCA_UMC_V2,	 HWID_MCATYPE(0x96, 0x1)	},
 	{ SMCA_USB,	 HWID_MCATYPE(0xAA, 0x0)	},

drivers/edac/mce_amd.c

@@ -690,7 +690,10 @@ static void decode_mc6_mce(struct mce *m)
 
 static const char * const smca_long_names[] = {
 	[SMCA_CS ... SMCA_CS_V2]	= "Coherent Station",
+	[SMCA_DACC_BE]			= "DACC Back-end Unit",
+	[SMCA_DACC_FE]			= "DACC Front-end Unit",
 	[SMCA_DE]			= "Decode Unit",
+	[SMCA_EDDR5CMN]			= "eDDR5 CMN Unit",
 	[SMCA_EX]			= "Execution Unit",
 	[SMCA_FP]			= "Floating Point Unit",
 	[SMCA_GMI_PCS]			= "Global Memory Interconnect PCS Unit",
@@ -700,17 +703,24 @@ static const char * const smca_long_names[] = {
 	[SMCA_L3_CACHE]			= "L3 Cache",
 	[SMCA_LS ... SMCA_LS_V2]	= "Load Store Unit",
 	[SMCA_MP5]			= "Microprocessor 5 Unit",
+	[SMCA_MPART]			= "MPART Unit",
+	[SMCA_MPASP ... SMCA_MPASP_V2]	= "MPASP Unit",
+	[SMCA_MPDACC]			= "MPDACC Unit",
 	[SMCA_MPDMA]			= "MPDMA Unit",
+	[SMCA_MPM]			= "MPM Unit",
+	[SMCA_MPRAS]			= "MPRAS Unit",
 	[SMCA_NBIF]			= "NBIF Unit",
 	[SMCA_NBIO]			= "Northbridge IO Unit",
 	[SMCA_PB]			= "Parameter Block",
 	[SMCA_PCIE ... SMCA_PCIE_V2]	= "PCI Express Unit",
+	[SMCA_PCIE_PL]			= "PCIe Link Unit",
 	[SMCA_PIE]			= "Power, Interrupts, etc.",
 	[SMCA_PSP ... SMCA_PSP_V2]	= "Platform Security Processor",
 	[SMCA_RESERVED]			= "Reserved",
 	[SMCA_SATA]			= "SATA Unit",
 	[SMCA_SHUB]			= "System Hub Unit",
 	[SMCA_SMU ... SMCA_SMU_V2]	= "System Management Unit",
+	[SMCA_SSBDCI]			= "Die to Die Interconnect Unit",
 
 	/* UMC v2 is separate because both of them can exist in a single system. */
 	[SMCA_UMC]			= "Unified Memory Controller",