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Merge tag 'v6.1-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

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Adapt emac nodes to make them conform to the newly yaml-converted binding.

* tag 'v6.1-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: restyle emac nodes
  ARM: dts: rockchip: fix rk3036 emac node compatible string

Link: https://lore.kernel.org/r/4766760.31r3eYUQgx@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2022-09-12 16:13:36 +02:00
parent b5a8826222 1dabb74971
commit b68ec1163c
7 changed files with 53 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm/boot/dts/rk3036-evb.dts
View File

@@ -15,16 +15,20 @@ memory@60000000 {
};
&emac {
phy = <&phy0>;
phy-reset-duration = <10>; /* millisecond */
phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
phy = <&phy0>;
phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
phy-reset-duration = <10>; /* millisecond */
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};

16
arch/arm/boot/dts/rk3036-kylin.dts
View File

@@ -80,16 +80,20 @@ &acodec {
};
&emac {
phy = <&phy0>;
phy-reset-duration = <10>; /* millisecond */
phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
phy = <&phy0>;
phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
phy-reset-duration = <10>; /* millisecond */
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};

4
arch/arm/boot/dts/rk3036.dtsi
View File

@@ -225,11 +225,9 @@ usb_host: usb@101c0000 {
};
emac: ethernet@10200000 {
compatible = "rockchip,rk3036-emac", "snps,arc-emac";
compatible = "rockchip,rk3036-emac";
reg = <0x10200000 0x4000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
rockchip,grf = <&grf>;
clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
clock-names = "hclk", "macref", "macclk";

17
arch/arm/boot/dts/rk3066a-marsboard.dts
View File

@@ -150,18 +150,21 @@ vcc28_cif: regulator@12 {
#include "tps65910.dtsi"
&emac {
status = "okay";
phy = <&phy0>;
phy-supply = <&vcc_rmii>;
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
};
};
};

15
arch/arm/boot/dts/rk3066a-rayeager.dts
View File

@@ -142,15 +142,20 @@ &cpu1 {
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
phy = <&phy0>;
phy-supply = <&vcc_rmii>;
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
};
};
};

21
arch/arm/boot/dts/rk3188-radxarock.dts
View File

@@ -126,18 +126,21 @@ vsys: vsys-regulator {
};
&emac {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
phy = <&phy0>;
phy-supply = <&vcc_rmii>;
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
};
};
};

2
arch/arm/boot/dts/rk3xxx.dtsi
View File

@@ -186,8 +186,6 @@ emac: ethernet@10204000 {
compatible = "snps,arc-emac";
reg = <0x10204000 0x3c>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
rockchip,grf = <&grf>;