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arm64: dts: msm8998: thermal: Fix the cpu sensor numbers

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The silver cluster (typically cpu0-3) are monitored by sensor IDs 1-3 on
tsens controller 0. The gold cluster (typically cpu4-7) are monitored by
sensor IDs 7-10 on tsens controller 0.

Fixes: 4449b6f248 ("arm64: dts: qcom: msm8998: Add tsens and thermal-zones")
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
This commit is contained in:
Amit Kucheria
2019-03-29 15:42:11 +05:30
committed by Andy Gross
parent 0f5f91f01c
commit b67d9c5d6f
1 changed files with 8 additions and 8 deletions
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16
arch/arm64/boot/dts/qcom/msm8998.dtsi
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@@ -342,7 +342,7 @@ cpu-thermal0 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 6>;
thermal-sensors = <&tsens0 1>;
trips {
cpu_alert0: trip0 {
@@ -363,7 +363,7 @@ cpu-thermal1 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
thermal-sensors = <&tsens0 2>;
trips {
cpu_alert1: trip0 {
@@ -384,7 +384,7 @@ cpu-thermal2 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
thermal-sensors = <&tsens0 3>;
trips {
cpu_alert2: trip0 {
@@ -405,7 +405,7 @@ cpu-thermal3 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 9>;
thermal-sensors = <&tsens0 4>;
trips {
cpu_alert3: trip0 {
@@ -426,7 +426,7 @@ cpu-thermal4 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
thermal-sensors = <&tsens0 7>;
trips {
cpu_alert4: trip0 {
@@ -447,7 +447,7 @@ cpu-thermal5 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 11>;
thermal-sensors = <&tsens0 8>;
trips {
cpu_alert5: trip0 {
@@ -468,7 +468,7 @@ cpu-thermal6 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 0>;
thermal-sensors = <&tsens0 9>;
trips {
cpu_alert6: trip0 {
@@ -489,7 +489,7 @@ cpu-thermal7 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 1>;
thermal-sensors = <&tsens0 10>;
trips {
cpu_alert7: trip0 {