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drm/i915/cx0: Pass crtc_state to intel_c20_compute_hdmi_tmds_pll()

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The variable crtc_state already contains everything that
intel_c20_compute_hdmi_tmds_pll() needs. Simplify the function's
signature by passing that struct instead of separate variables.

Suggested-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241023153352.144146-2-gustavo.sousa@intel.com
This commit is contained in:
Gustavo Sousa
2024-10-23 12:33:45 -03:00
committed by Matt Roper
parent 182a32bcc2
commit b67d84f25d
1 changed files with 6 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/drm/i915/display/intel_cx0_phy.c
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@@ -2159,8 +2159,9 @@ static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
}
static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_state *pll_state)
static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
{
struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20;
u64 datarate;
u64 mpll_tx_clk_div;
u64 vco_freq_shift;
@@ -2172,10 +2173,10 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_
u8 mpllb_ana_freq_vco;
u8 mpll_div_multiplier;
if (pixel_clock < 25175 || pixel_clock > 600000)
if (crtc_state->port_clock < 25175 || crtc_state->port_clock > 600000)
return -EINVAL;
datarate = ((u64)pixel_clock * 1000) * 10;
datarate = ((u64)crtc_state->port_clock * 1000) * 10;
mpll_tx_clk_div = ilog2(div64_u64((u64)CLOCK_9999MHZ, (u64)datarate));
vco_freq_shift = ilog2(div64_u64((u64)CLOCK_4999MHZ * (u64)256, (u64)datarate));
vco_freq = (datarate << vco_freq_shift) >> 8;
@@ -2197,7 +2198,7 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_
else
mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
pll_state->clock = pixel_clock;
pll_state->clock = crtc_state->port_clock;
pll_state->tx[0] = 0xbe88;
pll_state->tx[1] = 0x9800;
pll_state->tx[2] = 0x0000;
@@ -2287,8 +2288,7 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
/* try computed C20 HDMI tables before using consolidated tables */
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
if (intel_c20_compute_hdmi_tmds_pll(crtc_state->port_clock,
&crtc_state->dpll_hw_state.cx0pll.c20) == 0)
if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0)
return 0;
}