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drm/i915/adlp+/dp_mst: Align master transcoder disabling with spec wrt. DP2 config

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On ADLP+ during modeset disabling, disable the DP2 configuration for MST
master transcoders as required by the specification.

Bspec: 55424, 54128, 65448, 68849
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241030192313.4030617-6-imre.deak@intel.com
This commit is contained in:
Imre Deak
2024-10-30 21:23:13 +02:00
parent 90477f0dfd
commit b63937da16
1 changed files with 2 additions and 0 deletions
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drivers/gpu/drm/i915/display/intel_ddi.c
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@@ -3097,6 +3097,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false);
intel_ddi_config_transcoder_dp2(old_crtc_state, false);
/*
* From TGL spec: "If single stream or multi-stream master transcoder:
* Configure Transcoder Clock select to direct no clock to the