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pinctrl: renesas: rzg2l: Add support to configure slew-rate

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Add support to configure slew-rate property of the pin.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240530173857.164073-11-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar
2024-05-30 18:38:52 +01:00
committed by Geert Uytterhoeven
parent 7d566a4d27
commit b588b53b2c
1 changed files with 18 additions and 0 deletions
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18
drivers/pinctrl/renesas/pinctrl-rzg2l.c
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@@ -127,6 +127,7 @@
#define PFC(off) (0x0400 + (off) * 4)
#define PIN(off) (0x0800 + (off))
#define IOLH(off) (0x1000 + (off) * 8)
#define SR(off) (0x1400 + (off) * 8)
#define IEN(off) (0x1800 + (off) * 8)
#define ISEL(off) (0x2C00 + (off) * 8)
#define SD_CH(off, ch) ((off) + (ch) * 4)
@@ -145,6 +146,7 @@
#define PFC_MASK 0x07
#define IEN_MASK 0x01
#define IOLH_MASK 0x03
#define SR_MASK 0x01
#define PM_INPUT 0x1
#define PM_OUTPUT 0x2
@@ -1049,6 +1051,13 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
arg = ret;
break;
case PIN_CONFIG_SLEW_RATE:
if (!(cfg & PIN_CFG_SR))
return -EINVAL;
arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK);
break;
case PIN_CONFIG_DRIVE_STRENGTH: {
unsigned int index;
@@ -1155,6 +1164,15 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
settings.power_source = pinconf_to_config_argument(_configs[i]);
break;
case PIN_CONFIG_SLEW_RATE:
arg = pinconf_to_config_argument(_configs[i]);
if (!(cfg & PIN_CFG_SR) || arg > 1)
return -EINVAL;
rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
arg = pinconf_to_config_argument(_configs[i]);