mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-05 15:49:42 -04:00
ASoC: stm32: sai: add stm32mp25 support
Merge series from Olivier Moysan <olivier.moysan@foss.st.com>: Update STM32 SAI driver and binding to support STM32MP25 SoCs.
This commit is contained in:
@@ -20,6 +20,7 @@ properties:
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enum:
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- st,stm32f4-sai
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- st,stm32h7-sai
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- st,stm32mp25-sai
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reg:
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items:
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@@ -43,9 +44,11 @@ properties:
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const: 1
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clocks:
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minItems: 1
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maxItems: 3
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clock-names:
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minItems: 1
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maxItems: 3
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access-controllers:
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@@ -156,7 +159,13 @@ allOf:
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items:
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- const: x8k
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- const: x11k
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else:
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32mph7-sai
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then:
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properties:
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clocks:
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items:
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@@ -170,6 +179,21 @@ allOf:
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- const: x8k
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- const: x11k
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32mp25-sai
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then:
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properties:
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clocks:
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items:
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- description: pclk feeds the peripheral bus interface.
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clock-names:
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items:
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- const: pclk
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additionalProperties: false
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examples:
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@@ -19,26 +19,42 @@
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#include "stm32_sai.h"
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static int stm32_sai_get_parent_clk(struct stm32_sai_data *sai);
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static const struct stm32_sai_conf stm32_sai_conf_f4 = {
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.version = STM_SAI_STM32F4,
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.fifo_size = 8,
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.has_spdif_pdm = false,
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.get_sai_ck_parent = stm32_sai_get_parent_clk,
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};
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/*
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* Default settings for stm32 H7 socs and next.
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* Default settings for STM32H7x socs and STM32MP1x.
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* These default settings will be overridden if the soc provides
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* support of hardware configuration registers.
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* - STM32H7: rely on default settings
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* - STM32MP1: retrieve settings from registers
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*/
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static const struct stm32_sai_conf stm32_sai_conf_h7 = {
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.version = STM_SAI_STM32H7,
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.fifo_size = 8,
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.has_spdif_pdm = true,
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.get_sai_ck_parent = stm32_sai_get_parent_clk,
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};
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/*
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* STM32MP2x:
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* - do not use SAI parent clock source selection
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* - do not use DMA burst mode
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*/
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static const struct stm32_sai_conf stm32_sai_conf_mp25 = {
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.no_dma_burst = true,
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};
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static const struct of_device_id stm32_sai_ids[] = {
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{ .compatible = "st,stm32f4-sai", .data = (void *)&stm32_sai_conf_f4 },
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{ .compatible = "st,stm32h7-sai", .data = (void *)&stm32_sai_conf_h7 },
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{ .compatible = "st,stm32mp25-sai", .data = (void *)&stm32_sai_conf_mp25 },
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{}
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};
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@@ -148,6 +164,29 @@ static int stm32_sai_set_sync(struct stm32_sai_data *sai_client,
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return ret;
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}
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static int stm32_sai_get_parent_clk(struct stm32_sai_data *sai)
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{
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struct device *dev = &sai->pdev->dev;
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sai->clk_x8k = devm_clk_get(dev, "x8k");
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if (IS_ERR(sai->clk_x8k)) {
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if (PTR_ERR(sai->clk_x8k) != -EPROBE_DEFER)
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dev_err(dev, "missing x8k parent clock: %ld\n",
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PTR_ERR(sai->clk_x8k));
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return PTR_ERR(sai->clk_x8k);
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}
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sai->clk_x11k = devm_clk_get(dev, "x11k");
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if (IS_ERR(sai->clk_x11k)) {
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if (PTR_ERR(sai->clk_x11k) != -EPROBE_DEFER)
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dev_err(dev, "missing x11k parent clock: %ld\n",
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PTR_ERR(sai->clk_x11k));
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return PTR_ERR(sai->clk_x11k);
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}
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return 0;
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}
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static int stm32_sai_probe(struct platform_device *pdev)
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{
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struct stm32_sai_data *sai;
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@@ -160,6 +199,8 @@ static int stm32_sai_probe(struct platform_device *pdev)
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if (!sai)
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return -ENOMEM;
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sai->pdev = pdev;
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sai->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(sai->base))
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return PTR_ERR(sai->base);
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@@ -178,15 +219,11 @@ static int stm32_sai_probe(struct platform_device *pdev)
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"missing bus clock pclk\n");
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}
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sai->clk_x8k = devm_clk_get(&pdev->dev, "x8k");
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if (IS_ERR(sai->clk_x8k))
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return dev_err_probe(&pdev->dev, PTR_ERR(sai->clk_x8k),
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"missing x8k parent clock\n");
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sai->clk_x11k = devm_clk_get(&pdev->dev, "x11k");
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if (IS_ERR(sai->clk_x11k))
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return dev_err_probe(&pdev->dev, PTR_ERR(sai->clk_x11k),
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"missing x11k parent clock\n");
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if (sai->conf.get_sai_ck_parent) {
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ret = sai->conf.get_sai_ck_parent(sai);
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if (ret)
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return ret;
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}
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/* init irqs */
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sai->irq = platform_get_irq(pdev, 0);
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@@ -227,7 +264,6 @@ static int stm32_sai_probe(struct platform_device *pdev)
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}
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clk_disable_unprepare(sai->pclk);
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sai->pdev = pdev;
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sai->set_sync = &stm32_sai_set_sync;
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platform_set_drvdata(pdev, sai);
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@@ -264,16 +264,22 @@ enum stm32_sai_syncout {
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STM_SAI_SYNC_OUT_B,
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};
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struct stm32_sai_data;
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/**
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* struct stm32_sai_conf - SAI configuration
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* @get_sai_ck_parent: get parent clock of SAI kernel clock
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* @version: SAI version
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* @fifo_size: SAI fifo size as words number
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* @has_spdif_pdm: SAI S/PDIF and PDM features support flag
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* @no_dma_burst: Support only DMA single transfers if set
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*/
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struct stm32_sai_conf {
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int (*get_sai_ck_parent)(struct stm32_sai_data *sai);
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u32 version;
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u32 fifo_size;
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bool has_spdif_pdm;
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bool no_dma_burst;
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};
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/**
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@@ -60,6 +60,9 @@
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#define SAI_MCLK_NAME_LEN 32
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#define SAI_RATE_11K 11025
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#define SAI_MAX_SAMPLE_RATE_8K 192000
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#define SAI_MAX_SAMPLE_RATE_11K 176400
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#define SAI_CK_RATE_TOLERANCE 1000 /* ppm */
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/**
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* struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
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@@ -80,6 +83,7 @@
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* @dir: SAI block direction (playback or capture). set at init
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* @master: SAI block mode flag. (true=master, false=slave) set at init
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* @spdif: SAI S/PDIF iec60958 mode flag. set at init
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* @sai_ck_used: flag set while exclusivity on SAI kernel clock is active
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* @fmt: SAI block format. relevant only for custom protocols. set at init
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* @sync: SAI block synchronization mode. (none, internal or external)
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* @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
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@@ -93,6 +97,8 @@
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* @iec958: iec958 data
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* @ctrl_lock: control lock
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* @irq_lock: prevent race condition with IRQ
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* @set_sai_ck_rate: set SAI kernel clock rate
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* @put_sai_ck_rate: put SAI kernel clock rate
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*/
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struct stm32_sai_sub_data {
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struct platform_device *pdev;
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@@ -112,6 +118,7 @@ struct stm32_sai_sub_data {
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int dir;
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bool master;
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bool spdif;
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bool sai_ck_used;
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int fmt;
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int sync;
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int synco;
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@@ -125,6 +132,8 @@ struct stm32_sai_sub_data {
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struct snd_aes_iec958 iec958;
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struct mutex ctrl_lock; /* protect resources accessed by controls */
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spinlock_t irq_lock; /* used to prevent race condition with IRQ */
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int (*set_sai_ck_rate)(struct stm32_sai_sub_data *sai, unsigned int rate);
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void (*put_sai_ck_rate)(struct stm32_sai_sub_data *sai);
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};
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enum stm32_sai_fifo_th {
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@@ -351,8 +360,26 @@ static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai,
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return ret;
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}
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static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai,
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unsigned int rate)
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static bool stm32_sai_rate_accurate(unsigned int max_rate, unsigned int rate)
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{
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u64 delta, dividend;
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int ratio;
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ratio = DIV_ROUND_CLOSEST(max_rate, rate);
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if (!ratio)
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return false;
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dividend = mul_u32_u32(1000000, abs(max_rate - (ratio * rate)));
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delta = div_u64(dividend, max_rate);
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if (delta <= SAI_CK_RATE_TOLERANCE)
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return true;
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return false;
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}
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static int stm32_sai_set_parent_clk(struct stm32_sai_sub_data *sai,
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unsigned int rate)
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{
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struct platform_device *pdev = sai->pdev;
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struct clk *parent_clk = sai->pdata->clk_x8k;
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@@ -370,6 +397,92 @@ static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai,
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return ret;
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}
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static void stm32_sai_put_parent_rate(struct stm32_sai_sub_data *sai)
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{
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if (sai->sai_ck_used) {
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sai->sai_ck_used = false;
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clk_rate_exclusive_put(sai->sai_ck);
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}
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}
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static int stm32_sai_set_parent_rate(struct stm32_sai_sub_data *sai,
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unsigned int rate)
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{
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struct platform_device *pdev = sai->pdev;
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unsigned int sai_ck_rate, sai_ck_max_rate, sai_curr_rate, sai_new_rate;
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int div, ret;
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/*
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* Set maximum expected kernel clock frequency
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* - mclk on or spdif:
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* f_sai_ck = MCKDIV * mclk-fs * fs
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* Here typical 256 ratio is assumed for mclk-fs
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* - mclk off:
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* f_sai_ck = MCKDIV * FRL * fs
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* Where FRL=[8..256], MCKDIV=[1..n] (n depends on SAI version)
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* Set constraint MCKDIV * FRL <= 256, to ensure MCKDIV is in available range
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* f_sai_ck = sai_ck_max_rate * pow_of_two(FRL) / 256
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*/
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if (!(rate % SAI_RATE_11K))
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sai_ck_max_rate = SAI_MAX_SAMPLE_RATE_11K * 256;
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else
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sai_ck_max_rate = SAI_MAX_SAMPLE_RATE_8K * 256;
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if (!sai->sai_mclk && !STM_SAI_PROTOCOL_IS_SPDIF(sai))
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sai_ck_max_rate /= DIV_ROUND_CLOSEST(256, roundup_pow_of_two(sai->fs_length));
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/*
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* Request exclusivity, as the clock is shared by SAI sub-blocks and by
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* some SAI instances. This allows to ensure that the rate cannot be
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* changed while one or more SAIs are using the clock.
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*/
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clk_rate_exclusive_get(sai->sai_ck);
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sai->sai_ck_used = true;
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/*
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* Check current kernel clock rate. If it gives the expected accuracy
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* return immediately.
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*/
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sai_curr_rate = clk_get_rate(sai->sai_ck);
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if (stm32_sai_rate_accurate(sai_ck_max_rate, sai_curr_rate))
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return 0;
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/*
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* Otherwise try to set the maximum rate and check the new actual rate.
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* If the new rate does not give the expected accuracy, try to set
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* lower rates for the kernel clock.
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*/
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sai_ck_rate = sai_ck_max_rate;
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div = 1;
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do {
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/* Check new rate accuracy. Return if ok */
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sai_new_rate = clk_round_rate(sai->sai_ck, sai_ck_rate);
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if (stm32_sai_rate_accurate(sai_ck_rate, sai_new_rate)) {
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ret = clk_set_rate(sai->sai_ck, sai_ck_rate);
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if (ret) {
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dev_err(&pdev->dev, "Error %d setting sai_ck rate. %s",
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ret, ret == -EBUSY ?
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"Active stream rates may be in conflict\n" : "\n");
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goto err;
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}
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return 0;
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}
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/* Try a lower frequency */
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div++;
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sai_ck_rate = sai_ck_max_rate / div;
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} while (sai_ck_rate > rate);
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/* No accurate rate found */
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dev_err(&pdev->dev, "Failed to find an accurate rate");
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err:
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stm32_sai_put_parent_rate(sai);
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return -EINVAL;
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}
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static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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@@ -565,11 +678,15 @@ static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
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clk_rate_exclusive_put(sai->sai_mclk);
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sai->mclk_rate = 0;
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}
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if (sai->put_sai_ck_rate)
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sai->put_sai_ck_rate(sai);
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return 0;
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}
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/* If master clock is used, set parent clock now */
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ret = stm32_sai_set_parent_clock(sai, freq);
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/* If master clock is used, configure SAI kernel clock now */
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ret = sai->set_sai_ck_rate(sai, freq);
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if (ret)
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return ret;
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@@ -993,7 +1110,7 @@ static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
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int ret;
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if (!sai->sai_mclk) {
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ret = stm32_sai_set_parent_clock(sai, rate);
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ret = sai->set_sai_ck_rate(sai, rate);
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if (ret)
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return ret;
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}
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@@ -1154,6 +1271,14 @@ static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
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clk_disable_unprepare(sai->sai_ck);
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/*
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* Release kernel clock if following conditions are fulfilled
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* - Master clock is not used. Kernel clock won't be released trough sysclk
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* - Put handler is defined. Involve that clock is managed exclusively
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*/
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if (!sai->sai_mclk && sai->put_sai_ck_rate)
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sai->put_sai_ck_rate(sai);
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spin_lock_irqsave(&sai->irq_lock, flags);
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sai->substream = NULL;
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spin_unlock_irqrestore(&sai->irq_lock, flags);
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@@ -1188,7 +1313,7 @@ static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
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* constraints).
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*/
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sai->dma_params.maxburst = 4;
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if (sai->pdata->conf.fifo_size < 8)
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if (sai->pdata->conf.fifo_size < 8 || sai->pdata->conf.no_dma_burst)
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sai->dma_params.maxburst = 1;
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/* Buswidth will be set by framework at runtime */
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sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
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@@ -1526,6 +1651,13 @@ static int stm32_sai_sub_probe(struct platform_device *pdev)
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return -EINVAL;
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}
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if (sai->pdata->conf.get_sai_ck_parent) {
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sai->set_sai_ck_rate = stm32_sai_set_parent_clk;
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} else {
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sai->set_sai_ck_rate = stm32_sai_set_parent_rate;
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sai->put_sai_ck_rate = stm32_sai_put_parent_rate;
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}
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ret = stm32_sai_sub_parse_of(pdev, sai);
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if (ret)
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return ret;
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