mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-14 01:49:20 -04:00
arm64: dts: mediatek: mt8186: add lvts definitions
Values extracted from vendor source tree. Signed-off-by: Nicolas Pitre <npitre@baylibre.com> Link: https://lore.kernel.org/r/20240402032729.2736685-8-nico@fluxnic.net [Angelo: Fixed validation and quality issues] Signed-off-by: Julien Panis <jpanis@baylibre.com> Link: https://lore.kernel.org/r/20240603-mtk-thermal-mt818x-dtsi-v7-3-8c8e3c7a3643@baylibre.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
committed by
AngeloGioacchino Del Regno
parent
fe035fa6f5
commit
b3610c99f1
@@ -1361,6 +1361,17 @@ spi0: spi@1100a000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lvts: thermal-sensor@1100b000 {
|
||||
compatible = "mediatek,mt8186-lvts";
|
||||
reg = <0 0x1100b000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
|
||||
resets = <&infracfg_ao MT8186_INFRA_THERMAL_CTRL_RST>;
|
||||
nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
|
||||
nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
pwm0: pwm@1100e000 {
|
||||
compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
|
||||
reg = <0 0x1100e000 0 0x1000>;
|
||||
@@ -1676,6 +1687,14 @@ efuse: efuse@11cb0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
lvts_efuse_data1: lvts1-calib@1cc {
|
||||
reg = <0x1cc 0x14>;
|
||||
};
|
||||
|
||||
lvts_efuse_data2: lvts2-calib@2f8 {
|
||||
reg = <0x2f8 0x14>;
|
||||
};
|
||||
|
||||
gpu_speedbin: gpu-speedbin@59c {
|
||||
reg = <0x59c 0x4>;
|
||||
bits = <0 3>;
|
||||
|
||||
Reference in New Issue
Block a user