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arm64: dts: sprd: Split PMU nodes for heterogeneous CPUs

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Arm heterogeneous configurations should have separate PMU nodes for each
CPU uarch as the uarch specific events can be different. The
"arm,armv8-pmuv3" compatible is also intended for s/w models rather than
specific uarch implementations.

Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240412222923.3873814-1-robh@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Rob Herring
2024-04-12 17:29:22 -05:00
committed by Krzysztof Kozlowski
parent 1613e604df
commit b32e036a74
2 changed files with 20 additions and 8 deletions
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14
arch/arm64/boot/dts/sprd/ums512.dtsi
View File

@@ -136,16 +136,22 @@ timer {
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
};
pmu {
compatible = "arm,armv8-pmuv3";
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
};
pmu-a75 {
compatible = "arm,cortex-a75-pmu";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CPU6>, <&CPU7>;
};
soc: soc {

14
arch/arm64/boot/dts/sprd/ums9620.dtsi
View File

@@ -144,16 +144,22 @@ timer {
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
};
pmu {
compatible = "arm,armv8-pmuv3";
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>;
};
pmu-a76 {
compatible = "arm,cortex-a76-pmu";
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
};
soc: soc {