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net: macb: Set MDIO clock divisor for pclk higher than 160MHz

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Currently macb sets clock divisor for pclk up to 160 MHz.
Function gem_mdc_clk_div was updated to enable divisor
for higher values of pclk.

Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Bartosz Wawrzyniak
2023-03-16 10:03:39 +00:00
committed by David S. Miller
parent df28e8690e
commit b31587feaa
2 changed files with 7 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/ethernet/cadence/macb.h
View File

@@ -692,6 +692,8 @@
#define GEM_CLK_DIV48 3
#define GEM_CLK_DIV64 4
#define GEM_CLK_DIV96 5
#define GEM_CLK_DIV128 6
#define GEM_CLK_DIV224 7
/* Constants for MAN register */
#define MACB_MAN_C22_SOF 1

6
drivers/net/ethernet/cadence/macb_main.c
View File

@@ -2640,8 +2640,12 @@ static u32 gem_mdc_clk_div(struct macb *bp)
config = GEM_BF(CLK, GEM_CLK_DIV48);
else if (pclk_hz <= 160000000)
config = GEM_BF(CLK, GEM_CLK_DIV64);
else
else if (pclk_hz <= 240000000)
config = GEM_BF(CLK, GEM_CLK_DIV96);
else if (pclk_hz <= 320000000)
config = GEM_BF(CLK, GEM_CLK_DIV128);
else
config = GEM_BF(CLK, GEM_CLK_DIV224);
return config;
}