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spi: axiado: cond_no_effect and kernel-doc fixes
Babanpreet Singh <bbnpreetsingh@gmail.com> says:
Two small cleanups for the Axiado SPI driver, both defects present
since the driver was added in e75a6b00ad ("spi: axiado: Add driver
for Axiado SPI DB controller").
Patch 1 addresses the coccinelle cond_no_effect warning reported by
the kernel test robot on 2026-07-12 [1]: the RX-only/full-duplex
else-if arm and the trailing else arm in ax_transfer_one() have
identical bodies, so the second condition has no effect. The arms are
merged; no functional change (on x86_64/gcc 14, only
ax_transfer_one()'s object code changes, dropping the dead condition
evaluation).
Patch 2 fixes the kernel-doc comments in the driver: a copy-pasted
function name on ax_spi_get_rx_byte_for_irq(), a /** block with no
identifier line on ax_spi_process_rx_and_finalize(), and stale/missing
member documentation on struct ax_spi. This silences the driver's two
W=1 kernel-doc warnings plus five more visible when kernel-doc is run
on the header directly.
Both patches are against spi/for-next; they are independent of each
other except for touching the same file.
[1] https://lore.kernel.org/r/202607121827.djB0zLAj-lkp@intel.com/
Link: https://patch.msgid.link/20260713060807.7-1-bbnpreetsingh@gmail.com
This commit is contained in:
@@ -213,7 +213,7 @@ static void ax_spi_fill_tx_fifo(struct ax_spi *xspi)
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}
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/**
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* ax_spi_get_rx_byte - Gets a byte from the RX FIFO buffer
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* ax_spi_get_rx_byte_for_irq - Gets a byte from the RX FIFO buffer
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* @xspi: Controller private data (struct ax_spi *)
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*
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* This function handles the logic of extracting bytes from the 32-bit RX FIFO.
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@@ -246,9 +246,13 @@ static u8 ax_spi_get_rx_byte_for_irq(struct ax_spi *xspi)
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}
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/**
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* ax_spi_process_rx_and_finalize - Process RX bytes and check for completion
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* @ctlr: Pointer to spi_controller structure
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*
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* Helper function to process received bytes and check for transfer completion.
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* This avoids code duplication and centralizes the completion logic.
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* Returns true if the transfer was finalized.
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*
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* Return: true if the transfer was finalized.
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*/
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static bool ax_spi_process_rx_and_finalize(struct spi_controller *ctlr)
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{
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@@ -430,15 +434,11 @@ static int ax_transfer_one(struct spi_controller *ctlr,
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/* TX mode: discard all received data */
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xspi->rx_discard = transfer->len;
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xspi->rx_copy_remaining = 0;
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} else if ((!transfer->tx_buf && transfer->rx_buf) ||
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(transfer->tx_buf && transfer->rx_buf)) {
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/* RX mode: generate clock by filling TX FIFO with dummy bytes
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* Full-duplex mode: generate clock by filling TX FIFO
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*/
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xspi->rx_discard = 0;
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xspi->rx_copy_remaining = transfer->len;
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} else {
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/* No TX and RX */
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/* RX-only or full-duplex mode: copy received data, with the
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* clock generated by filling the TX FIFO (with dummy bytes
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* in RX-only mode)
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*/
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xspi->rx_discard = 0;
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xspi->rx_copy_remaining = transfer->len;
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}
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@@ -98,9 +98,10 @@
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* @regs: Virtual address of the SPI controller registers
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* @ref_clk: Pointer to the peripheral clock
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* @pclk: Pointer to the APB clock
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* @clk_rate: Reference clock rate in Hz
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* @speed_hz: Current SPI bus clock speed in Hz
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* @txbuf: Pointer to the TX buffer
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* @rxbuf: Pointer to the RX buffer
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* @tx_buf: Pointer to the TX buffer
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* @rx_buf: Pointer to the RX buffer
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* @tx_bytes: Number of bytes left to transfer
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* @rx_bytes: Number of bytes requested
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* @tx_fifo_depth: Depth of the TX FIFO
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