spi: axiado: cond_no_effect and kernel-doc fixes

Babanpreet Singh <bbnpreetsingh@gmail.com> says:

Two small cleanups for the Axiado SPI driver, both defects present
since the driver was added in e75a6b00ad ("spi: axiado: Add driver
for Axiado SPI DB controller").

Patch 1 addresses the coccinelle cond_no_effect warning reported by
the kernel test robot on 2026-07-12 [1]: the RX-only/full-duplex
else-if arm and the trailing else arm in ax_transfer_one() have
identical bodies, so the second condition has no effect. The arms are
merged; no functional change (on x86_64/gcc 14, only
ax_transfer_one()'s object code changes, dropping the dead condition
evaluation).

Patch 2 fixes the kernel-doc comments in the driver: a copy-pasted
function name on ax_spi_get_rx_byte_for_irq(), a /** block with no
identifier line on ax_spi_process_rx_and_finalize(), and stale/missing
member documentation on struct ax_spi. This silences the driver's two
W=1 kernel-doc warnings plus five more visible when kernel-doc is run
on the header directly.

Both patches are against spi/for-next; they are independent of each
other except for touching the same file.

[1] https://lore.kernel.org/r/202607121827.djB0zLAj-lkp@intel.com/

Link: https://patch.msgid.link/20260713060807.7-1-bbnpreetsingh@gmail.com
This commit is contained in:
Mark Brown
2026-07-19 23:55:50 +01:00
2 changed files with 13 additions and 12 deletions

View File

@@ -213,7 +213,7 @@ static void ax_spi_fill_tx_fifo(struct ax_spi *xspi)
}
/**
* ax_spi_get_rx_byte - Gets a byte from the RX FIFO buffer
* ax_spi_get_rx_byte_for_irq - Gets a byte from the RX FIFO buffer
* @xspi: Controller private data (struct ax_spi *)
*
* This function handles the logic of extracting bytes from the 32-bit RX FIFO.
@@ -246,9 +246,13 @@ static u8 ax_spi_get_rx_byte_for_irq(struct ax_spi *xspi)
}
/**
* ax_spi_process_rx_and_finalize - Process RX bytes and check for completion
* @ctlr: Pointer to spi_controller structure
*
* Helper function to process received bytes and check for transfer completion.
* This avoids code duplication and centralizes the completion logic.
* Returns true if the transfer was finalized.
*
* Return: true if the transfer was finalized.
*/
static bool ax_spi_process_rx_and_finalize(struct spi_controller *ctlr)
{
@@ -430,15 +434,11 @@ static int ax_transfer_one(struct spi_controller *ctlr,
/* TX mode: discard all received data */
xspi->rx_discard = transfer->len;
xspi->rx_copy_remaining = 0;
} else if ((!transfer->tx_buf && transfer->rx_buf) ||
(transfer->tx_buf && transfer->rx_buf)) {
/* RX mode: generate clock by filling TX FIFO with dummy bytes
* Full-duplex mode: generate clock by filling TX FIFO
*/
xspi->rx_discard = 0;
xspi->rx_copy_remaining = transfer->len;
} else {
/* No TX and RX */
/* RX-only or full-duplex mode: copy received data, with the
* clock generated by filling the TX FIFO (with dummy bytes
* in RX-only mode)
*/
xspi->rx_discard = 0;
xspi->rx_copy_remaining = transfer->len;
}

View File

@@ -98,9 +98,10 @@
* @regs: Virtual address of the SPI controller registers
* @ref_clk: Pointer to the peripheral clock
* @pclk: Pointer to the APB clock
* @clk_rate: Reference clock rate in Hz
* @speed_hz: Current SPI bus clock speed in Hz
* @txbuf: Pointer to the TX buffer
* @rxbuf: Pointer to the RX buffer
* @tx_buf: Pointer to the TX buffer
* @rx_buf: Pointer to the RX buffer
* @tx_bytes: Number of bytes left to transfer
* @rx_bytes: Number of bytes requested
* @tx_fifo_depth: Depth of the TX FIFO