arm: dts: arm: Drop redundant fixed-factor clocks

There's not much reason to have multiple fixed-factor-clock instances
which are all the same factor and clock input. Drop the nodes, but keep
the labels to minimize the changes and keep some distinction of the
different clocks.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/20240528191536.1444649-1-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20240627-arm-dts-fixes-v1-1-40a2cb7d344b@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Rob Herring
2024-06-27 21:57:38 +02:00
committed by Arnd Bergmann
parent f7e642bcd6
commit b1a4e71d4f
6 changed files with 6 additions and 198 deletions

View File

@@ -53,7 +53,7 @@ vmmc: fixedregulator@0 {
regulator-boot-on;
};
xtal24mhz: xtal24mhz@24M {
xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
@@ -67,46 +67,6 @@ timclk: timclk@1M {
clocks = <&xtal24mhz>;
};
mclk: mclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
kmiclk: kmiclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
sspclk: sspclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
uartclk: uartclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
wdogclk: wdogclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
/* FIXME: this actually hangs off the PLL clocks */
pclk: pclk@0 {
#clock-cells = <0>;

View File

@@ -63,7 +63,7 @@ veth: regulator-veth {
regulator-boot-on;
};
xtal24mhz: xtal24mhz@24M {
xtal24mhz: mclk: kmiclk: sspclk: uartclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
@@ -77,38 +77,6 @@ timclk: timclk@1M {
clocks = <&xtal24mhz>;
};
mclk: mclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
kmiclk: kmiclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
sspclk: sspclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
uartclk: uartclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
/* FIXME: this actually hangs off the PLL clocks */
pclk: pclk@0 {
#clock-cells = <0>;

View File

@@ -163,7 +163,7 @@ veth: regulator-veth {
regulator-boot-on;
};
xtal24mhz: xtal24mhz@24M {
xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
@@ -183,46 +183,6 @@ timclk: timclk@1M {
clocks = <&xtal24mhz>;
};
mclk: mclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
kmiclk: kmiclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
sspclk: sspclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
uartclk: uartclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
wdogclk: wdogclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
/* FIXME: this actually hangs off the PLL clocks */
pclk: pclk@0 {
#clock-cells = <0>;

View File

@@ -62,7 +62,7 @@ veth: regulator-veth {
regulator-boot-on;
};
xtal24mhz: xtal24mhz@24M {
xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
@@ -82,46 +82,6 @@ timclk: timclk@1M {
clocks = <&xtal24mhz>;
};
mclk: mclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
kmiclk: kmiclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
sspclk: sspclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
uartclk: uartclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
wdogclk: wdogclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
/* FIXME: this actually hangs off the PLL clocks */
pclk: pclk@0 {
#clock-cells = <0>;

View File

@@ -57,20 +57,12 @@ chosen {
};
/* 24 MHz chrystal on the Integrator/AP development board */
xtal24mhz: xtal24mhz@24M {
xtal24mhz: pclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
pclk: pclk@0 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
/* The UART clock is 14.74 MHz divided by an ICS525 */
uartclk: uartclk@14.74M {
#clock-cells = <0>;

View File

@@ -78,7 +78,7 @@ spicfgclk: clk-spicfg {
clock-frequency = <75000000>;
};
sysclk: clk-sys {
sysclk: spiclcd: spicon: i2cclcd: i2caud: clock-sys {
compatible = "fixed-factor-clock";
clocks = <&oscclk0>;
#clock-cells = <0>;
@@ -102,38 +102,6 @@ audsclk: clk-auds {
clock-mult = <1>;
};
spiclcd: clk-cpiclcd {
compatible = "fixed-factor-clock";
clocks = <&oscclk0>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
};
spicon: clk-spicon {
compatible = "fixed-factor-clock";
clocks = <&oscclk0>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
};
i2cclcd: clk-i2cclcd {
compatible = "fixed-factor-clock";
clocks = <&oscclk0>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
};
i2caud: clk-i2caud {
compatible = "fixed-factor-clock";
clocks = <&oscclk0>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
};
soc {
compatible = "simple-bus";
ranges;