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drm/i915: Ensure no conflicts with BIOS when updating Dbuf

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TGL BIOS seems to enable both DBuf slices ocasionally, depending
how many displays are connected, while i915 according to BSpec
was powering on S1 DBuf slice, until a modeset was done.

This was causing a brief flash during the boot as we were
disabling slice, previously used by BIOS with that.

To prevent this, now we are ensuring tht we are enabling
_at least_ one slice, but if there are more, let's not
power them off.

Fixes: ff2cd8635e ("drm/i915: Correctly map DBUF slices to pipes")
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200213140412.32697-2-stanislav.lisovskiy@intel.com
This commit is contained in:
Stanislav Lisovskiy
2020-02-13 16:04:10 +02:00
committed by Jani Nikula
parent 1fc1e8d4f4
commit b18e249bf6
1 changed files with 4 additions and 2 deletions
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6
drivers/gpu/drm/i915/display/intel_display_power.c
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@@ -4470,11 +4470,13 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
{
skl_ddb_get_hw_state(dev_priv);
/*
* Just power up 1 slice, we will
* Just power up at least 1 slice, we will
* figure out later which slices we have and what we need.
*/
icl_dbuf_slices_update(dev_priv, BIT(DBUF_S1));
icl_dbuf_slices_update(dev_priv, dev_priv->enabled_dbuf_slices_mask |
BIT(DBUF_S1));
}
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)