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drm/amd/powerplay: implement smu send message functions for smu11 (v3)
Add function of smu send message for smu11 v2: fix the missing ) in define of smu_send_smc_msg_with_param v3: Use adev usec timeout for smu as well, the origin time 10 us is not enough. (Ray) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -52,6 +52,9 @@ struct smu_funcs
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int (*write_watermarks_table)(struct smu_context *smu);
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int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
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int (*system_features_control)(struct smu_context *smu, bool en);
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int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
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int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
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};
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#define smu_init_microcode(smu) \
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@@ -90,7 +93,10 @@ struct smu_funcs
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((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
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#define smu_system_features_control(smu, en) \
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((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
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#define smu_send_smc_msg(smu, msg) \
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((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
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#define smu_send_smc_msg_with_param(smu, msg, param) \
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((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
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extern const struct amd_ip_funcs smu_ip_funcs;
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@@ -26,9 +26,91 @@
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#include "amdgpu_smu.h"
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#include "smu_v11_0.h"
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#include "smu_v11_0_ppsmc.h"
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#include "soc15_common.h"
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#include "asic_reg/thm/thm_11_0_2_offset.h"
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#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
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#include "asic_reg/mp/mp_9_0_offset.h"
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#include "asic_reg/mp/mp_9_0_sh_mask.h"
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#include "asic_reg/nbio/nbio_7_4_offset.h"
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MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
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static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
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uint16_t msg)
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{
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struct amdgpu_device *adev = smu->adev;
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
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return 0;
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}
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static int smu_v11_0_wait_for_response(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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uint32_t cur_value, i;
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for (i = 0; i < adev->usec_timeout; i++) {
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cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
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if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
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break;
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udelay(1);
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}
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/* timeout means wrong logic */
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if (i == adev->usec_timeout)
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return -ETIME;
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return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == PPSMC_Result_OK ? 0:-EIO;
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}
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static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
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{
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struct amdgpu_device *adev = smu->adev;
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int ret = 0;
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smu_v11_0_wait_for_response(smu);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
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smu_v11_0_send_msg_without_waiting(smu, msg);
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ret = smu_v11_0_wait_for_response(smu);
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if (ret)
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pr_err("Failed to send message 0x%x, response 0x%x\n", msg,
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ret);
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return ret;
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}
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static int
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smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
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uint32_t param)
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{
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struct amdgpu_device *adev = smu->adev;
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int ret = 0;
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ret = smu_v11_0_wait_for_response(smu);
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if (ret)
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pr_err("Failed to send message 0x%x, response 0x%x\n", msg,
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ret);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
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smu_v11_0_send_msg_without_waiting(smu, msg);
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ret = smu_v11_0_wait_for_response(smu);
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if (ret)
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pr_err("Failed to send message 0x%x, response 0x%x\n", msg,
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ret);
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return ret;
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}
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static int smu_v11_0_init_microcode(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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@@ -93,6 +175,8 @@ static const struct smu_funcs smu_v11_0_funcs = {
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.init_microcode = smu_v11_0_init_microcode,
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.load_microcode = smu_v11_0_load_microcode,
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.check_fw_status = smu_v11_0_check_fw_status,
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.send_smc_msg = smu_v11_0_send_msg,
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.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
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};
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void smu_v11_0_set_smu_funcs(struct smu_context *smu)
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