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riscv: dts: starfive: add assigned-clock* to limit frquency

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In JH7110 SoC, we need to go by-pass mode, so we need add the
assigned-clock* properties to limit clock frquency.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
William Qiu
2023-09-22 14:28:34 +08:00
committed by Conor Dooley
parent be326bee09
commit af571133f7
1 changed files with 4 additions and 0 deletions
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4
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
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@@ -250,6 +250,8 @@ &i2stx1 {
&mmc0 {
max-frequency = <100000000>;
assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
assigned-clock-rates = <50000000>;
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
@@ -266,6 +268,8 @@ &mmc0 {
&mmc1 {
max-frequency = <100000000>;
assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
assigned-clock-rates = <50000000>;
bus-width = <4>;
no-sdio;
no-mmc;