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drm/amdgpu/pm: add smu i2c implementation for navi1x (v5)

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And handle more than just EEPROMs.

v2: fix restart handling between transactions.
v3: handle 7 to 8 bit addr conversion
v4: Fix &req --> req. (Luben T)
v5: squash in i2c channel fix

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
This commit is contained in:
Alex Deucher
2021-01-21 14:17:34 -05:00
parent f400b6cec8
commit af01340bc4
1 changed files with 116 additions and 0 deletions
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116
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
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@@ -2735,6 +2735,120 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
return sizeof(struct gpu_metrics_v1_3);
}
static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg *msgs, int num)
{
struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
struct smu_table_context *smu_table = &adev->smu.smu_table;
struct smu_table *table = &smu_table->driver_table;
SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
u16 bytes_to_transfer, remaining_bytes, msg_bytes;
u16 available_bytes = MAX_SW_I2C_COMMANDS;
int i, j, r, c;
u8 slave;
/* only support a single slave addr per transaction */
slave = msgs[0].addr;
for (i = 0; i < num; i++) {
if (slave != msgs[i].addr)
return -EINVAL;
bytes_to_transfer += min(msgs[i].len, available_bytes);
available_bytes -= bytes_to_transfer;
}
req = kzalloc(sizeof(*req), GFP_KERNEL);
if (!req)
return -ENOMEM;
req->I2CcontrollerPort = 0;
req->I2CSpeed = I2C_SPEED_FAST_400K;
req->SlaveAddress = slave << 1; /* 8 bit addresses */
req->NumCmds = bytes_to_transfer;
remaining_bytes = bytes_to_transfer;
c = 0;
for (i = 0; i < num; i++) {
struct i2c_msg *msg = &msgs[i];
msg_bytes = min(msg->len, remaining_bytes);
for (j = 0; j < msg_bytes; j++) {
SwI2cCmd_t *cmd = &req->SwI2cCmds[c++];
remaining_bytes--;
if (!(msg[i].flags & I2C_M_RD)) {
/* write */
cmd->CmdConfig |= I2C_CMD_WRITE;
cmd->RegisterAddr = msg->buf[j];
}
if ((msg[i].flags & I2C_M_STOP) ||
(!remaining_bytes))
cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
if ((i > 0) && !(msg[i].flags & I2C_M_NOSTART))
cmd->CmdConfig |= CMDCONFIG_RESTART_BIT;
}
}
mutex_lock(&adev->smu.mutex);
r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
mutex_unlock(&adev->smu.mutex);
if (r)
goto fail;
remaining_bytes = bytes_to_transfer;
c = 0;
for (i = 0; i < num; i++) {
struct i2c_msg *msg = &msgs[i];
msg_bytes = min(msg->len, remaining_bytes);
for (j = 0; j < msg_bytes; j++) {
SwI2cCmd_t *cmd = &res->SwI2cCmds[c++];
remaining_bytes--;
if (msg[i].flags & I2C_M_RD)
msg->buf[j] = cmd->Data;
}
}
r = bytes_to_transfer;
fail:
kfree(req);
return r;
}
static u32 navi10_i2c_func(struct i2c_adapter *adap)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
static const struct i2c_algorithm navi10_i2c_algo = {
.master_xfer = navi10_i2c_xfer,
.functionality = navi10_i2c_func,
};
static int navi10_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
{
struct amdgpu_device *adev = to_amdgpu_device(control);
int res;
control->owner = THIS_MODULE;
control->class = I2C_CLASS_SPD;
control->dev.parent = &adev->pdev->dev;
control->algo = &navi10_i2c_algo;
snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
res = i2c_add_adapter(control);
if (res)
DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
return res;
}
static void navi10_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
{
i2c_del_adapter(control);
}
static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
void **table)
{
@@ -3078,6 +3192,8 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.set_default_dpm_table = navi10_set_default_dpm_table,
.dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
.dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
.i2c_init = navi10_i2c_control_init,
.i2c_fini = navi10_i2c_control_fini,
.print_clk_levels = navi10_print_clk_levels,
.force_clk_levels = navi10_force_clk_levels,
.populate_umd_state_clk = navi10_populate_umd_state_clk,