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pinctrl: Use IRQ trigger mask helpers

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Use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH instead of open-coded
trigger type combinations in irqchip callbacks.

No functional change intended.

Assisted-by: Claude:claude-sonnet-5
Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Maulik Shah
2026-08-02 19:35:43 +05:30
committed by Linus Walleij
parent d4f32b8b8a
commit aef612f013
9 changed files with 12 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/pinctrl/actions/pinctrl-owl.c
View File

@@ -824,7 +824,7 @@ static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type)
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(data, handle_level_irq);
else
irq_set_handler_locked(data, handle_edge_irq);

2
drivers/pinctrl/airoha/pinctrl-airoha.c
View File

@@ -2435,7 +2435,7 @@ static int airoha_irq_type(struct irq_data *data, unsigned int type)
if (gpiochip->irq_type[data->hwirq])
return 0;
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
type = IRQ_TYPE_EDGE_BOTH;
}
gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK;

4
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
View File

@@ -159,7 +159,7 @@ static void nsp_gpio_irq_ack(struct irq_data *d)
u32 trigger_type;
trigger_type = irq_get_trigger_type(d->irq);
if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
if (trigger_type & IRQ_TYPE_EDGE_BOTH)
writel(val, chip->base + NSP_GPIO_EVENT);
}
@@ -177,7 +177,7 @@ static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
u32 trigger_type;
trigger_type = irq_get_trigger_type(d->irq);
if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
if (trigger_type & IRQ_TYPE_EDGE_BOTH)
nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
else
nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);

2
drivers/pinctrl/mediatek/mtk-eint.c
View File

@@ -216,7 +216,7 @@ static int mtk_eint_set_type(struct irq_data *d, unsigned int type)
writel(mask, reg);
}
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
if (type & IRQ_TYPE_EDGE_BOTH) {
reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr);
writel(mask, reg);
} else {

5
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
View File

@@ -260,11 +260,10 @@ static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)
return -EINVAL;
}
if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
if (type & IRQ_TYPE_LEVEL_MASK) {
npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
irq_set_handler_locked(d, handle_level_irq);
} else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING)) {
} else if (type & IRQ_TYPE_EDGE_BOTH) {
npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
irq_set_handler_locked(d, handle_edge_irq);
}

2
drivers/pinctrl/pinctrl-ocelot.c
View File

@@ -2317,7 +2317,7 @@ static const struct irq_chip ocelot_irqchip = {
static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)
{
if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_chip_handler_name_locked(data, &ocelot_level_irqchip,
handle_level_irq, NULL);
if (type & IRQ_TYPE_EDGE_BOTH)

2
drivers/pinctrl/pinctrl-sx150x.c
View File

@@ -525,7 +525,7 @@ static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
unsigned int n, val = 0;
if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
if (flow_type & IRQ_TYPE_LEVEL_MASK)
return -EINVAL;
n = irqd_to_hwirq(d);

4
drivers/pinctrl/qcom/pinctrl-msm.c
View File

@@ -1181,9 +1181,9 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
else if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(d, handle_edge_irq);
return 0;

2
drivers/pinctrl/spear/pinctrl-plgpio.c
View File

@@ -339,7 +339,7 @@ static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
if (plgpio->regs.eit == -1)
supported_type = IRQ_TYPE_LEVEL_HIGH;
else
supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
supported_type = IRQ_TYPE_EDGE_BOTH;
if (!(trigger & supported_type))
return -EINVAL;