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synced 2026-04-03 12:16:22 -04:00
cxl/port: Arrange for always synchronous endpoint attach
Make it so that upon return from devm_cxl_add_endpoint() that cxl_mem_probe() can assume that the endpoint has had a chance to complete cxl_port_probe(). I.e. cxl_port module loading has completed prior to device registration. Delete the MODULE_SOFTDEP() as it is not sufficient for this purpose, but a hard link-time dependency is reliable. Specifically MODULE_SOFTDEP() does not guarantee that the module loading has completed prior to the completion of the current module's init. Cc: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> Cc: Alejandro Lucero <alucerop@amd.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Tested-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Tested-by: Alejandro Lucero <alucerop@amd.com> Link: https://patch.msgid.link/20251216005616.3090129-4-dan.j.williams@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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@@ -780,6 +780,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host,
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struct cxl_dport *parent_dport);
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struct cxl_root *devm_cxl_add_root(struct device *host,
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const struct cxl_root_ops *ops);
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int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
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struct cxl_dport *parent_dport);
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struct cxl_root *find_cxl_root(struct cxl_port *port);
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DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_device(&_T->port.dev))
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@@ -45,44 +45,6 @@ static int cxl_mem_dpa_show(struct seq_file *file, void *data)
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return 0;
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}
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static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
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struct cxl_dport *parent_dport)
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{
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struct cxl_port *parent_port = parent_dport->port;
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struct cxl_port *endpoint, *iter, *down;
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int rc;
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/*
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* Now that the path to the root is established record all the
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* intervening ports in the chain.
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*/
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for (iter = parent_port, down = NULL; !is_cxl_root(iter);
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down = iter, iter = to_cxl_port(iter->dev.parent)) {
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struct cxl_ep *ep;
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ep = cxl_ep_load(iter, cxlmd);
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ep->next = down;
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}
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/* Note: endpoint port component registers are derived from @cxlds */
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endpoint = devm_cxl_add_port(host, &cxlmd->dev, CXL_RESOURCE_NONE,
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parent_dport);
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if (IS_ERR(endpoint))
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return PTR_ERR(endpoint);
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rc = cxl_endpoint_autoremove(cxlmd, endpoint);
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if (rc)
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return rc;
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if (!endpoint->dev.driver) {
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dev_err(&cxlmd->dev, "%s failed probe\n",
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dev_name(&endpoint->dev));
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return -ENXIO;
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}
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return 0;
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}
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static int cxl_debugfs_poison_inject(void *data, u64 dpa)
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{
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struct cxl_memdev *cxlmd = data;
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@@ -275,8 +237,3 @@ MODULE_DESCRIPTION("CXL: Memory Expansion");
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MODULE_LICENSE("GPL v2");
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MODULE_IMPORT_NS("CXL");
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MODULE_ALIAS_CXL(CXL_DEVICE_MEMORY_EXPANDER);
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/*
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* create_endpoint() wants to validate port driver attach immediately after
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* endpoint registration.
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*/
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MODULE_SOFTDEP("pre: cxl_port");
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@@ -156,10 +156,50 @@ static struct cxl_driver cxl_port_driver = {
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.probe = cxl_port_probe,
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.id = CXL_DEVICE_PORT,
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.drv = {
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.probe_type = PROBE_FORCE_SYNCHRONOUS,
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.dev_groups = cxl_port_attribute_groups,
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},
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};
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int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
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struct cxl_dport *parent_dport)
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{
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struct cxl_port *parent_port = parent_dport->port;
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struct cxl_port *endpoint, *iter, *down;
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int rc;
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/*
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* Now that the path to the root is established record all the
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* intervening ports in the chain.
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*/
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for (iter = parent_port, down = NULL; !is_cxl_root(iter);
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down = iter, iter = to_cxl_port(iter->dev.parent)) {
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struct cxl_ep *ep;
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ep = cxl_ep_load(iter, cxlmd);
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ep->next = down;
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}
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/* Note: endpoint port component registers are derived from @cxlds */
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endpoint = devm_cxl_add_port(host, &cxlmd->dev, CXL_RESOURCE_NONE,
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parent_dport);
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if (IS_ERR(endpoint))
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return PTR_ERR(endpoint);
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rc = cxl_endpoint_autoremove(cxlmd, endpoint);
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if (rc)
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return rc;
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if (!endpoint->dev.driver) {
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dev_err(&cxlmd->dev, "%s failed probe\n",
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dev_name(&endpoint->dev));
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return -ENXIO;
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}
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return 0;
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}
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EXPORT_SYMBOL_FOR_MODULES(devm_cxl_add_endpoint, "cxl_mem");
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static int __init cxl_port_init(void)
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{
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return cxl_driver_register(&cxl_port_driver);
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