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drm/amd: add AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU debug mask

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Kernel parameter `no_console_suspend` is required to capture all
hibernation kernel log via serial console. But when the parameter
is set, GPU will be resumed in thaw stage. This causes many issues
on alinux3 kernel.

Fix: add new debug mask `AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU` to
replace the check of `console_suspend_enabled` in thaw() callback.
User can enable it using `amdgpu.debug_mask=0x800`.

Signed-off-by: Samuel Zhang <guoqing.zhang@amd.com>
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Samuel Zhang
2026-06-11 11:18:07 +08:00
committed by Alex Deucher
parent 97bcaf15ad
commit ae16ca815d
2 changed files with 10 additions and 3 deletions
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1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View File

@@ -1136,6 +1136,7 @@ struct amdgpu_device {
bool debug_vm_userptr;
bool debug_disable_ce_logs;
bool debug_enable_ce_cs;
bool debug_hibernation_thaw_resume_gpu;
/* Protection for the following isolation structure */
struct mutex enforce_isolation_mutex;

12
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View File

@@ -33,7 +33,6 @@
#include <drm/drm_vblank.h>
#include <linux/cc_platform.h>
#include <linux/console.h>
#include <linux/dynamic_debug.h>
#include <linux/module.h>
#include <linux/mmu_notifier.h>
@@ -146,7 +145,8 @@ enum AMDGPU_DEBUG_MASK {
AMDGPU_DEBUG_SMU_POOL = BIT(7),
AMDGPU_DEBUG_VM_USERPTR = BIT(8),
AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9),
AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10)
AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10),
AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU = BIT(11),
};
unsigned int amdgpu_vram_limit = UINT_MAX;
@@ -2291,6 +2291,11 @@ static void amdgpu_init_debug_options(struct amdgpu_device *adev)
pr_info("debug: allowing command submission to CE engine\n");
adev->debug_enable_ce_cs = true;
}
if (amdgpu_debug_mask & AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU) {
pr_info("debug: resume gpu in thaw() of hibernation\n");
adev->debug_hibernation_thaw_resume_gpu = true;
}
}
static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)
@@ -2705,9 +2710,10 @@ static int amdgpu_pmops_freeze(struct device *dev)
static int amdgpu_pmops_thaw(struct device *dev)
{
struct drm_device *drm_dev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(drm_dev);
/* do not resume device if it's normal hibernation */
if (console_suspend_enabled &&
if (!adev->debug_hibernation_thaw_resume_gpu &&
!pm_hibernate_is_recovering() &&
!pm_hibernation_mode_is_suspend())
return 0;