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net: ngbe: move mdio access registers to libwx

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Registers of mdio accessing are common defined in libwx, remove the
redundant macro definitions in ngbe driver.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jiawen Wu
2023-08-23 14:19:35 +08:00
committed by David S. Miller
parent 02b2a6f91b
commit ad63f7aa58
2 changed files with 42 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

84
drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.c
View File

@@ -37,24 +37,24 @@ static int ngbe_phy_read_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int regn
wr32(wx, NGBE_MDIO_CLAUSE_SELECT, 0xF);
/* setup and write the address cycle command */
command = NGBE_MSCA_RA(regnum) |
NGBE_MSCA_PA(phy_addr) |
NGBE_MSCA_DA(device_type);
wr32(wx, NGBE_MSCA, command);
command = NGBE_MSCC_CMD(NGBE_MSCA_CMD_READ) |
NGBE_MSCC_BUSY |
NGBE_MDIO_CLK(6);
wr32(wx, NGBE_MSCC, command);
command = WX_MSCA_RA(regnum) |
WX_MSCA_PA(phy_addr) |
WX_MSCA_DA(device_type);
wr32(wx, WX_MSCA, command);
command = WX_MSCC_CMD(WX_MSCA_CMD_READ) |
WX_MSCC_BUSY |
WX_MDIO_CLK(6);
wr32(wx, WX_MSCC, command);
/* wait to complete */
ret = read_poll_timeout(rd32, val, !(val & NGBE_MSCC_BUSY), 1000,
100000, false, wx, NGBE_MSCC);
ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000,
100000, false, wx, WX_MSCC);
if (ret) {
wx_err(wx, "Mdio read c22 command did not complete.\n");
return ret;
}
return (u16)rd32(wx, NGBE_MSCC);
return (u16)rd32(wx, WX_MSCC);
}
static int ngbe_phy_write_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
@@ -65,19 +65,19 @@ static int ngbe_phy_write_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int reg
wr32(wx, NGBE_MDIO_CLAUSE_SELECT, 0xF);
/* setup and write the address cycle command */
command = NGBE_MSCA_RA(regnum) |
NGBE_MSCA_PA(phy_addr) |
NGBE_MSCA_DA(device_type);
wr32(wx, NGBE_MSCA, command);
command = WX_MSCA_RA(regnum) |
WX_MSCA_PA(phy_addr) |
WX_MSCA_DA(device_type);
wr32(wx, WX_MSCA, command);
command = value |
NGBE_MSCC_CMD(NGBE_MSCA_CMD_WRITE) |
NGBE_MSCC_BUSY |
NGBE_MDIO_CLK(6);
wr32(wx, NGBE_MSCC, command);
WX_MSCC_CMD(WX_MSCA_CMD_WRITE) |
WX_MSCC_BUSY |
WX_MDIO_CLK(6);
wr32(wx, WX_MSCC, command);
/* wait to complete */
ret = read_poll_timeout(rd32, val, !(val & NGBE_MSCC_BUSY), 1000,
100000, false, wx, NGBE_MSCC);
ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000,
100000, false, wx, WX_MSCC);
if (ret)
wx_err(wx, "Mdio write c22 command did not complete.\n");
@@ -92,24 +92,24 @@ static int ngbe_phy_read_reg_mdi_c45(struct mii_bus *bus, int phy_addr, int devn
wr32(wx, NGBE_MDIO_CLAUSE_SELECT, 0x0);
/* setup and write the address cycle command */
command = NGBE_MSCA_RA(regnum) |
NGBE_MSCA_PA(phy_addr) |
NGBE_MSCA_DA(devnum);
wr32(wx, NGBE_MSCA, command);
command = NGBE_MSCC_CMD(NGBE_MSCA_CMD_READ) |
NGBE_MSCC_BUSY |
NGBE_MDIO_CLK(6);
wr32(wx, NGBE_MSCC, command);
command = WX_MSCA_RA(regnum) |
WX_MSCA_PA(phy_addr) |
WX_MSCA_DA(devnum);
wr32(wx, WX_MSCA, command);
command = WX_MSCC_CMD(WX_MSCA_CMD_READ) |
WX_MSCC_BUSY |
WX_MDIO_CLK(6);
wr32(wx, WX_MSCC, command);
/* wait to complete */
ret = read_poll_timeout(rd32, val, !(val & NGBE_MSCC_BUSY), 1000,
100000, false, wx, NGBE_MSCC);
ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000,
100000, false, wx, WX_MSCC);
if (ret) {
wx_err(wx, "Mdio read c45 command did not complete.\n");
return ret;
}
return (u16)rd32(wx, NGBE_MSCC);
return (u16)rd32(wx, WX_MSCC);
}
static int ngbe_phy_write_reg_mdi_c45(struct mii_bus *bus, int phy_addr,
@@ -121,19 +121,19 @@ static int ngbe_phy_write_reg_mdi_c45(struct mii_bus *bus, int phy_addr,
wr32(wx, NGBE_MDIO_CLAUSE_SELECT, 0x0);
/* setup and write the address cycle command */
command = NGBE_MSCA_RA(regnum) |
NGBE_MSCA_PA(phy_addr) |
NGBE_MSCA_DA(devnum);
wr32(wx, NGBE_MSCA, command);
command = WX_MSCA_RA(regnum) |
WX_MSCA_PA(phy_addr) |
WX_MSCA_DA(devnum);
wr32(wx, WX_MSCA, command);
command = value |
NGBE_MSCC_CMD(NGBE_MSCA_CMD_WRITE) |
NGBE_MSCC_BUSY |
NGBE_MDIO_CLK(6);
wr32(wx, NGBE_MSCC, command);
WX_MSCC_CMD(WX_MSCA_CMD_WRITE) |
WX_MSCC_BUSY |
WX_MDIO_CLK(6);
wr32(wx, WX_MSCC, command);
/* wait to complete */
ret = read_poll_timeout(rd32, val, !(val & NGBE_MSCC_BUSY), 1000,
100000, false, wx, NGBE_MSCC);
ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000,
100000, false, wx, WX_MSCC);
if (ret)
wx_err(wx, "Mdio write c45 command did not complete.\n");

19
drivers/net/ethernet/wangxun/ngbe/ngbe_type.h
View File

@@ -59,25 +59,6 @@
#define NGBE_EEPROM_VERSION_L 0x1D
#define NGBE_EEPROM_VERSION_H 0x1E
/* mdio access */
#define NGBE_MSCA 0x11200
#define NGBE_MSCA_RA(v) FIELD_PREP(U16_MAX, v)
#define NGBE_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v)
#define NGBE_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v)
#define NGBE_MSCC 0x11204
#define NGBE_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v)
enum NGBE_MSCA_CMD_value {
NGBE_MSCA_CMD_RSV = 0,
NGBE_MSCA_CMD_WRITE,
NGBE_MSCA_CMD_POST_READ,
NGBE_MSCA_CMD_READ,
};
#define NGBE_MSCC_SADDR BIT(18)
#define NGBE_MSCC_BUSY BIT(22)
#define NGBE_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v)
/* Media-dependent registers. */
#define NGBE_MDIO_CLAUSE_SELECT 0x11220