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drm/i915/chv: Implement WaDisableSemaphoreAndSyncFlipWait:chv

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BDW has the same requirement but the w/a database doens't list
this w/a for BDW. Seems to be another one of those "stick a bunch
of known workarounds into this bag and write something on the label"
type of things.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä
2014-04-09 13:28:36 +03:00
committed by Daniel Vetter
parent 232ce3374f
commit acea6f9573
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/drm/i915/intel_pm.c
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@@ -5389,6 +5389,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
I915_WRITE(GEN7_FF_THREAD_MODE,
I915_READ(GEN7_FF_THREAD_MODE) &
~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
/* WaDisableSemaphoreAndSyncFlipWait:chv */
I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
}
static void g4x_init_clock_gating(struct drm_device *dev)