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drm/amdgpu/ras: Add debug mask to disable CE logs for uniras

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Add debug mask to disable kernel logs of RAS correctable errors,
including both ACA and CE error counter kernel messages.

Signed-off-by: Ce Sun <cesun102@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ce Sun
2026-07-15 09:35:12 +08:00
committed by Alex Deucher
parent b208b0c446
commit ac9c371515
6 changed files with 24 additions and 8 deletions
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1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
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@@ -223,6 +223,7 @@ extern int amdgpu_smartshift_bias;
extern int amdgpu_use_xgmi_p2p;
extern int amdgpu_mtype_local;
extern int amdgpu_enforce_isolation;
extern uint amdgpu_debug_mask;
#ifdef CONFIG_HSA_AMD
extern int sched_policy;
extern bool debug_evictions;

1
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
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@@ -309,6 +309,7 @@ static struct ras_core_context *amdgpu_ras_mgr_create_ras_core(struct amdgpu_dev
amdgpu_ras_mgr_eeprom_is_supported(adev);
init_config.poison_supported =
amdgpu_ras_is_poison_mode_supported(adev);
init_config.ras_debug_mask = amdgpu_debug_mask;
amdgpu_ras_mgr_init_aca_config(adev, &init_config);
amdgpu_ras_mgr_init_eeprom_config(adev, &init_config);

2
drivers/gpu/drm/amd/ras/rascore/ras.h
View File

@@ -301,6 +301,7 @@ struct ras_core_config {
bool poison_supported;
bool ras_eeprom_supported;
uint ras_debug_mask;
const struct ras_sys_func *sys_fn;
struct ras_aca_config aca_cfg;
@@ -403,4 +404,5 @@ int ras_core_convert_soc_pa_to_cur_nps_pages(struct ras_core_context *ras_core,
int ras_core_check_address_sanity(struct ras_core_context *ras_core, uint64_t addr);
int ras_core_set_debug_mode(struct ras_core_context *ras_core, bool enable);
bool ras_core_is_ce_log_disabled(struct ras_core_context *ras_core);
#endif

17
drivers/gpu/drm/amd/ras/rascore/ras_aca.c
View File

@@ -83,22 +83,20 @@ static void aca_report_ecc_info(struct ras_core_context *ras_core,
seq_no, skt, aid, ecc_count.total_ue_count, blk_name(blk));
}
if (ecc_count.new_de_count) {
if (ecc_count.new_de_count && blk == RAS_BLOCK_ID__UMC) {
RAS_DEV_INFO(ras_core->dev,
"{%llu} socket: %d, die: %d, %u new %s detected in %s block\n",
"{%llu} socket: %d, die: %d, %u new deferred hardware errors detected in %s block\n",
seq_no, skt, aid, ecc_count.new_de_count,
(blk == RAS_BLOCK_ID__UMC) ?
"deferred hardware errors" : "poison consumption",
blk_name(blk));
RAS_DEV_INFO(ras_core->dev,
"{%llu} socket: %d, die: %d, %u %s detected in total in %s block\n",
"{%llu} socket: %d, die: %d, %u deferred hardware errors detected in total in %s block\n",
seq_no, skt, aid, ecc_count.total_de_count,
(blk == RAS_BLOCK_ID__UMC) ?
"deferred hardware errors" : "poison consumption",
blk_name(blk));
}
if (ecc_count.new_ce_count) {
if (ras_core_is_ce_log_disabled(ras_core))
return;
RAS_DEV_INFO(ras_core->dev,
"{%llu} socket: %d, die: %d, %u new correctable hardware errors detected in %s block\n",
seq_no, skt, aid, ecc_count.new_ce_count, blk_name(blk));
@@ -114,6 +112,11 @@ static void aca_bank_log(struct ras_core_context *ras_core,
{
int i;
if (ras_core_is_ce_log_disabled(ras_core) &&
bank->ecc_type == RAS_ERR_TYPE__CE &&
!bank_ecc->de_count)
return;
RAS_DEV_INFO(ras_core->dev,
"{%llu}" RAS_HW_ERR "Accelerator Check Architecture events logged\n",
bank->seq_no);

2
drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c
View File

@@ -265,7 +265,7 @@ static int aca_parse_bank_default(struct ras_core_context *ras_core,
ecc->bank_info.addr = bank->regs[ACA_REG_IDX__ADDR];
if (aca_check_bank_is_de(ras_core, status)) {
ecc->de_count = 0;
ecc->de_count = 1;
} else {
if (bank->ecc_type == RAS_ERR_TYPE__UE)
ecc->ue_count = 1;

9
drivers/gpu/drm/amd/ras/rascore/ras_core.c
View File

@@ -28,6 +28,10 @@
#define IS_LEAP_YEAR(x) ((x % 4 == 0 && x % 100 != 0) || x % 400 == 0)
enum RAS_DEBUG_MASK {
RAS_DEBUG_DISABLE_RAS_CE_LOG = 9,
};
static const char * const ras_block_name[] = {
"umc",
"sdma",
@@ -545,6 +549,11 @@ bool ras_core_is_enabled(struct ras_core_context *ras_core)
return ras_core->ras_core_enabled;
}
bool ras_core_is_ce_log_disabled(struct ras_core_context *ras_core)
{
return !!(ras_core->config->ras_debug_mask & BIT(RAS_DEBUG_DISABLE_RAS_CE_LOG));
}
uint64_t ras_core_get_utc_second_timestamp(struct ras_core_context *ras_core)
{
if (!ras_core)