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drm/i915/dsc: Adding the new registers for DSC

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Adding new DSC register which are introducted MTL onwards

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230309062855.393087-4-suraj.kandpal@intel.com
This commit is contained in:
Suraj Kandpal
2023-03-09 11:58:51 +05:30
committed by Uma Shankar
parent 5011f2915b
commit ac754358c6
1 changed files with 28 additions and 0 deletions
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28
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
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@@ -46,6 +46,32 @@
_ICL_PIPE_DSS_CTL2_PB, \
_ICL_PIPE_DSS_CTL2_PC)
/* MTL Display Stream Compression registers */
#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB 0x782B4
#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB 0x783B4
#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC 0x784B4
#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC 0x785B4
#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
_MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
_MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
#define DSC_SL_BPG_OFFSET(offset) ((offset) << 27)
#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB 0x782B8
#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB 0x783B8
#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC 0x784B8
#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC 0x785B8
#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
_MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
_MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
#define DSC_NSL_BPG_OFFSET(offset) ((offset) << 16)
#define DSC_SL_OFFSET_ADJ(offset) ((offset) << 0)
/* Icelake Display Stream Compression Registers */
#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
@@ -59,6 +85,8 @@
#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
#define DSC_NATIVE_422_ENABLE BIT(23)
#define DSC_NATIVE_420_ENABLE BIT(22)
#define DSC_ALT_ICH_SEL (1 << 20)
#define DSC_VBR_ENABLE (1 << 19)
#define DSC_422_ENABLE (1 << 18)