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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-08-30 11:03:07 -04:00
pinctrl: airoha: an7583: fix muxing of non-gpio default pins
Current an7583 pinmux implementation have following issues:
* pins 51 and 52 can't be set as pcie_reset, current pcie_reset code
will sets pins to gpio mode instead.
* there is no proper way to set pins 41--54 to gpio mode.
* pins 41--53 can't be actually set as pwm pins. These pins must be
muxed to gpio mode as well.
This patch fixes above issues.
Fixes: 3ffeb17a9a ("pinctrl: airoha: add support for Airoha AN7583 PINs")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Mikhail Kshevetskiy
committed by
Linus Walleij
Linus Walleij
parent
da64ec8b4d
commit
aaa41d8010
@@ -85,6 +85,18 @@
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#define GPIO_SPI_CS1_MODE_MASK BIT(0)
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#define REG_GPIO_PON_MODE 0x021c
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#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26)
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#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25)
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#define AN7583_UART_RXD_GPIO_MODE_MASK BIT(24)
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#define AN7583_UART_TXD_GPIO_MODE_MASK BIT(23)
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#define AN7583_SPI_MISO_GPIO_MODE_MASK BIT(22)
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#define AN7583_SPI_MOSI_GPIO_MODE_MASK BIT(21)
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#define AN7583_SPI_CS_GPIO_MODE_MASK BIT(20)
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#define AN7583_SPI_CLK_GPIO_MODE_MASK BIT(19)
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#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18)
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#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17)
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#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16)
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#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15)
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#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
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#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
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#define GPIO_PCIE_RESET2_MASK BIT(12)
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@@ -783,6 +795,10 @@ static const int an7583_gpio45_pins[] = { 47 };
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static const int an7583_gpio46_pins[] = { 48 };
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static const int an7583_gpio47_pins[] = { 49 };
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static const int an7583_gpio48_pins[] = { 50 };
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static const int an7583_gpio49_pins[] = { 51 };
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static const int an7583_gpio50_pins[] = { 52 };
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static const int an7583_gpio51_pins[] = { 53 };
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static const int an7583_gpio52_pins[] = { 54 };
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static const int an7583_pcie_reset0_pins[] = { 51 };
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static const int an7583_pcie_reset1_pins[] = { 52 };
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@@ -863,6 +879,10 @@ static const struct pingroup an7583_pinctrl_groups[] = {
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PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
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PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
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PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
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PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
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PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
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PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
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PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
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PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
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PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
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};
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@@ -892,6 +912,11 @@ static const char *const pnand_groups[] = { "pnand" };
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static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
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static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
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"pcie_reset2" };
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static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41",
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"gpio42", "gpio43", "gpio44",
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"gpio45", "gpio46", "gpio47",
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"gpio48", "gpio49", "gpio50",
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"gpio51", "gpio52" };
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static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
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static const char *const pwm_groups[] = { "gpio0", "gpio1",
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"gpio2", "gpio3",
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@@ -938,7 +963,8 @@ static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
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"gpio42", "gpio43",
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"gpio44", "gpio45",
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"gpio46", "gpio47",
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"gpio48" };
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"gpio48", "gpio49",
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"gpio50", "gpio51" };
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static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
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"gpio35", "gpio42" };
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static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
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@@ -1484,6 +1510,36 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
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},
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};
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static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
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AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
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AN7583_I2C0_SCL_GPIO_MODE_MASK),
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AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
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AN7583_I2C0_SDA_GPIO_MODE_MASK),
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AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
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AN7583_I2C1_SCL_GPIO_MODE_MASK),
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AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
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AN7583_I2C1_SDA_GPIO_MODE_MASK),
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AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
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AN7583_SPI_CLK_GPIO_MODE_MASK),
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AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
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AN7583_SPI_CS_GPIO_MODE_MASK),
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AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
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AN7583_SPI_MOSI_GPIO_MODE_MASK),
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AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
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AN7583_SPI_MISO_GPIO_MODE_MASK),
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AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
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AN7583_UART_TXD_GPIO_MODE_MASK),
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AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
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AN7583_UART_RXD_GPIO_MODE_MASK),
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AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
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GPIO_PCIE_RESET0_MASK),
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AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
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GPIO_PCIE_RESET1_MASK),
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AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
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AN7583_MDC_0_GPIO_MODE_MASK),
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AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
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};
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static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
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{
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.name = "pcie_reset0",
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@@ -1491,7 +1547,7 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
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AIROHA_FUNC_MUX,
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REG_GPIO_PON_MODE,
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GPIO_PCIE_RESET0_MASK,
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GPIO_PCIE_RESET0_MASK
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0
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},
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.regmap_size = 1,
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}, {
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@@ -1500,7 +1556,7 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
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AIROHA_FUNC_MUX,
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REG_GPIO_PON_MODE,
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GPIO_PCIE_RESET1_MASK,
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GPIO_PCIE_RESET1_MASK
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0
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},
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.regmap_size = 1,
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},
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@@ -1637,16 +1693,32 @@ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
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AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT("gpio48", GPIO48_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
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AN7583_I2C0_SCL_GPIO_MODE_MASK),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
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AN7583_I2C0_SDA_GPIO_MODE_MASK),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
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AN7583_I2C1_SCL_GPIO_MODE_MASK),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
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AN7583_I2C1_SDA_GPIO_MODE_MASK),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
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AN7583_SPI_CLK_GPIO_MODE_MASK),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
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AN7583_SPI_CS_GPIO_MODE_MASK),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
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AN7583_SPI_MOSI_GPIO_MODE_MASK),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
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AN7583_SPI_MISO_GPIO_MODE_MASK),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
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AN7583_UART_TXD_GPIO_MODE_MASK),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
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AN7583_UART_RXD_GPIO_MODE_MASK),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
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GPIO_PCIE_RESET0_MASK),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
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GPIO_PCIE_RESET1_MASK),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
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AN7583_MDC_0_GPIO_MODE_MASK),
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};
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#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
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@@ -1901,6 +1973,7 @@ static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
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PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
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PINCTRL_FUNC_DESC("emmc", emmc),
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PINCTRL_FUNC_DESC("pnand", pnand),
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PINCTRL_FUNC_DESC("gpio", an7583_gpio),
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PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
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PINCTRL_FUNC_DESC("pwm", an7583_pwm),
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PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
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