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arm64: tegra: Fix #address-cells/#size-cells for SRAM on Tegra186

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The standard mmio-sram bindings require the #address- and #size-cells
properties to be 1.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
2019-12-22 14:59:02 +01:00
parent a10b9a2075
commit aa78032cab
1 changed files with 5 additions and 5 deletions
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10
arch/arm64/boot/dts/nvidia/tegra186.dtsi
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@@ -1216,20 +1216,20 @@ gpu@17000000 {
sysram@30000000 {
compatible = "nvidia,tegra186-sysram", "mmio-sram";
reg = <0x0 0x30000000 0x0 0x50000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x30000000 0x50000>;
cpu_bpmp_tx: shmem@4e000 {
compatible = "nvidia,tegra186-bpmp-shmem";
reg = <0x0 0x4e000 0x0 0x1000>;
reg = <0x4e000 0x1000>;
label = "cpu-bpmp-tx";
pool;
};
cpu_bpmp_rx: shmem@4f000 {
compatible = "nvidia,tegra186-bpmp-shmem";
reg = <0x0 0x4f000 0x0 0x1000>;
reg = <0x4f000 0x1000>;
label = "cpu-bpmp-rx";
pool;
};